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Timing analysis and CDC

Why are the write and read pointers of an asynchronous FIFO converted to Gray code before being synchronized into the other domain?

  1. ABecause Gray code halves the number of bits, so fewer synchronizers are needed
  2. BBecause only one bit changes per increment, so even if captured mid-change the result is the correct value from before or after the increment
  3. CBecause Gray-coded signals do not go metastable, so synchronization becomes unnecessary
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Answer: B. Because only one bit changes per increment, so even if captured mid-change the result is the correct value from before or after the increment

A binary pointer can change multiple bits at once, as in 0111 to 1000, so synchronizing each bit separately can yield a completely unrelated value. With Gray code only one bit changes per increment, so even if that bit goes metastable and resolves to either the old or new value, the result is the value from before or after the increment. The receiver merely sees a slightly stale value, so the FIFO does not break. The number of bits does not change, and metastability itself can still occur, so synchronizers are still required.

Asynchronous FIFO structure Write side (wclk) Read side (rclk) Dual-port RAM R/W on two clocks Write data Write pointer To Gray code Read data Read pointer To Gray code 2-FF sync Empty check 2-FF sync Full check Gray-code pointer In Gray code, only 1 bit changes per increment
Asynchronous FIFO structure · View in diagrams
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More Timing analysis and CDC questions

  1. What is the 4-bit binary value 0110 (decimal 6) converted to Gray code?
  2. In a 16-word-deep asynchronous FIFO, why are the write and read pointers made 5 bits, one bit more than the address?
  3. In a 16-word-deep asynchronous FIFO with 5-bit Gray code pointers, what is the correct condition for detecting full on the write side?
  4. In an asynchronous FIFO, the other side's pointer is used after synchronization, so the pointer value seen is 2–3 cycles stale. What effect does this delay have on full/empty detection?
  5. In an asynchronous FIFO with a 100 MHz write side and an 80 MHz read side, the write side writes a 100-word burst at one word per cycle and the read side reads one word per cycle. There is ample idle time between bursts. What is the minimum depth needed to avoid overflow (ignore synchronization delay)?