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Timing analysis and CDC

Why can it be a problem to leave the paths that carry an asynchronous FIFO's Gray code pointers to the other domain unconstrained (false path) just because they are asynchronous?

  1. ABecause setting a false path causes the synchronizer flip-flops to be removed by logic synthesis
  2. BBecause if the delay difference between bits exceeds the pointer update interval, the assumption that only one bit changes at a time breaks down on the receiving side
  3. CBecause setting a false path causes the tool to convert the pointer back to binary
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Answer: B. Because if the delay difference between bits exceeds the pointer update interval, the assumption that only one bit changes at a time breaks down on the receiving side

Gray code pointers assume that, at whichever receiving edge they are sampled, no more than one bit is changing. If the paths are left unconstrained, place and route can produce widely varying delays between bits. For example, with a 2 ns sending period, if the bit that changes first takes 3 ns to arrive and the bit that changes second takes 1 ns, both arrive at time 3 ns, so it looks as if two bits changed simultaneously. Therefore a maximum delay constraint is applied to keep the delay difference within one sending-clock period.

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More Timing analysis and CDC questions

  1. In a synchronous circuit with a clock period of 2.0 ns, the launching flip-flop's clock-to-output delay is 0.2 ns, the combinational logic delay is 1.4 ns and the capturing flip-flop's setup time is 0.1 ns. With zero clock skew, what is the setup slack?
  2. On a flip-flop-to-flip-flop path, the clock-to-output delay is 0.15 ns, the maximum combinational logic delay is 2.2 ns and the setup time is 0.15 ns. Ignoring skew and clock uncertainty, what is the maximum clock frequency at which this path can operate?
  3. Which correctly describes WNS and TNS as they appear in STA reports?
  4. A path has a clock period of 1.0 ns, a clock-to-output delay of 0.1 ns, a combinational logic delay of 0.85 ns and a setup time of 0.08 ns. If the clock arrives at the capturing flip-flop 0.05 ns later than at the launching flip-flop, what is the setup slack?
  5. When the clock arrives at the capturing flip-flop later than at the launching flip-flop (positive skew), what is the effect on setup and hold?