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Timing analysis and CDC

For which path is it appropriate to set a false path (set_false_path)?

  1. AA path that is structurally connected but along which no signal can actually propagate, for example because the select conditions are mutually exclusive
  2. BA path with a large timing violation that is hard to fix
  3. CA path that only needs to capture data once every two cycles
Show answer and explanation

Answer: A. A path that is structurally connected but along which no signal can actually propagate, for example because the select conditions are mutually exclusive

STA examines every connected path without considering what the logic means. As a result, violations can be reported even on paths that are never actually exercised, such as in a circuit where two multiplexers driven by the same select signal choose opposite inputs. Such paths are designated false paths and excluded from analysis. Excluding a path just because it is hard to fix hides real bugs. A path that captures once every two cycles should stay in the analysis as a multicycle path with extended time.

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More Timing analysis and CDC questions

  1. With a 2.0 ns clock at 50% duty cycle, a path launches on the rising edge and captures on the falling edge. With a setup time of 0.1 ns and zero skew, what is the maximum allowed sum of the clock-to-output delay and combinational logic delay?
  2. With a 2.0 ns clock, a path runs from a flip-flop that launches data on the rising edge at time 0 to a latch that opens (becomes transparent) at 1.0 ns and closes at 2.0 ns. If the data arrives at the latch at 1.4 ns, how much time has been borrowed at this latch (time borrowing)?
  3. In a circuit that stops the clock with a two-input AND gate of the clock and an enable signal, what does the STA clock gating check verify?
  4. With a 2.0 ns clock, set_input_delay 0.6 ns is set on an input port. If the internal flip-flop's setup time is 0.1 ns and clock latency and skew are ignored, what is the maximum delay allowed for the on-chip path from the input port to the flip-flop?
  5. What does the value specified with set_output_delay represent?