What Is an ASIC? Custom Chips vs CPUs and FPGAs Explained

14 min read · Updated: October 23, 2026

An ASIC (say "AY-sik") is a chip designed and made for one fixed job only. For that job, it is faster and uses less power than a CPU, which can run anything. But it cannot do other jobs, and it costs a lot before production can even start. That is why ASICs suit products made in large numbers.

What you'll learn

  • What an ASIC is, and where you already use one
  • Why a dedicated chip is faster and needs less power
  • How the "one-time cost" works, and why making more chips pays off
  • The steps to make an ASIC, and a way to share prototype costs
  • How an ASIC differs from a CPU, GPU and FPGA, and from an ASSP

Prerequisites: it helps to know that a chip (integrated circuit) is a circuit of transistors and wires built on one piece of silicon. "What Is an Integrated Circuit?" explains this.

In everyday life

Video on your phone is squeezed into a small amount of data so it is easy to send. To play it, the phone must keep turning that data back into the original picture. On many phones, a dedicated circuit does this work. In 2023, for example, Apple said it had added such a circuit to the iPhone 15 Pro's chip. It turns video in a format called AV1 back into pictures.

Dedicated chips also work behind web search and translation. In 2016, Google revealed the TPU, a chip it designed in-house for AI calculations. Bitcoin "mining" machines also contain chips that can do only that one calculation.

A chip like this, made for one job, is called an ASIC. A dedicated circuit inside part of a chip, like the phone's video circuit, follows the same idea. This article looks at why anyone builds a dedicated chip, and how it is made.

What is an ASIC? A chip designed for one job

ASIC stands for Application-Specific Integrated Circuit. As the name says, it is an integrated circuit (IC) designed for a fixed use.

The opposite idea is a general-purpose chip that can be used for anything. The best-known example is the CPU. Change its program, and it can do math, edit documents or run games ("What Is a CPU?"). An ASIC narrows its use from the start. In return, it does that one job extremely well.

How wide "one job" is depends on the chip. Some ASICs repeat almost a single kind of calculation. Others pack many functions into one design for one product. What they share is that each is made only for its intended use.

Where are ASICs used?

  • Bitcoin mining: Bitcoin repeats a calculation that turns data into a number of fixed length, searching for an answer that meets a condition. This calculation is a kind of hash function called SHA-256. Canaan says it shipped ASIC-based mining machines in January 2013, and that they were the world's first.
  • AI: Google's TPU is a chip focused on the "multiply and add" math that AI uses. When Google announced it in 2016, it had already been running in data centers for more than a year.
  • Video: Besides the video circuits in phone chips, there are dedicated chips for data centers. In a 2021 paper, Google reported a dedicated chip for converting video from one format to another.
  • Networking: These are the chips inside switches, the devices in data centers that send each piece of data toward where it is going. In 2022, Broadcom announced it was shipping a chip called Tomahawk 5. A single chip handles 51.2 terabits of data per second (1 tera is 1 trillion).
  • Cars: In 2019, Tesla described a chip it designed in-house for its driver-assistance features. It did so at Hot Chips, a chip conference. Tesla said it kept each chip's power under 40 W.

Part 1: Why a dedicated chip is faster and uses less power

A CPU fetches instructions, the written steps of a job, from memory one at a time and carries them out. It fetches, decodes, calculates and stores the result. This lets it handle any job, but every step adds work beyond the calculation itself.

An ASIC turns the steps of the job into the shape of the circuit itself. Data simply flows through calculation circuits lined up in a fixed order. There is no work spent decoding instructions, and no unused circuits. Many copies of the same calculation circuit can also sit side by side and run at once.

The first TPU shows how big the effect can be. In a 2017 article, Google compared it with the CPUs and GPUs then used in the same data centers. The TPU ran 15 to 30 times faster than them. In performance per watt, it was 30 to 80 times better. But the comparison covered only one task: having an already trained AI produce answers.

So "faster" and "less power" apply to the job chosen at design time. An ASIC basically cannot do any other job.

Part 2: The upfront cost and the cost per chip

ASIC costs are easier to understand when split in two. The first is a cost paid only once at the start, however many chips you make. It is called NRE, short for Non-Recurring Engineering, which means "engineering cost that does not repeat."

NRE is made up of three main things. First, the salaries of the many engineers who spend a long time designing and checking the chip. Second, license fees for design software and for circuit designs made by other companies. Third, the cost of making the master plates that carry the circuit patterns (masks).

Roughly speaking, a chip needs one mask for each of its layers. A 2022 article by the research firm SemiAnalysis says leading-edge chips have more than 60 layers. That makes a full mask set very expensive. On top of that, a mask set belongs to one design and cannot be reused for any other chip.

The second cost is paid for every chip you make. Circuits are built on a round silicon disk (a wafer), cut apart, and put into a case that connects them to the outside (a package). Then each chip is tested. An ASIC has no unneeded circuits, so it can be small, and this cost stays low.

The cost per chip is the NRE divided by the number made, plus the cost of making one. The next numbers are made up just to show the math. Say the NRE is $30 million and making one chip costs $5. Make only 10,000 chips, and each costs about $3,000. Make 10 million, and the cost per chip drops to $8.

The more chips you make, the smaller each chip's share of the upfront cost, so the cost per chip falls Cost per chip Upfront share Making cost Few Medium Many Chips made →
The cost of making one chip (the lower part) stays about the same however many you make. The one-time upfront cost (the upper part) shrinks per chip as you make more. Left out: real amounts and scale (the bar heights are only for illustration), and the way materials also get cheaper in large volumes.

In short, whether an ASIC pays off depends heavily on how many you make. That is why ASICs suit products that sell tens of millions of units, or companies like Google that use huge numbers themselves. If you make only a few, an off-the-shelf CPU or an FPGA, whose circuit can be rewritten later, costs less. You can see where the line falls between them in the chart in "What Is an FPGA?"

Part 3: How an ASIC is made

The overall design flow of an ASIC is much the same as for other chips (see "How an IC is made" in "What Is an Integrated Circuit?"). Here we focus on the points that matter most for ASICs.

How an ASIC is made: from the spec to RTL, logic synthesis, place and route, verification, tape-out, manufacturing and prototype testing Design Fab ① Set the spec ② Write it in RTL ③ Logic synthesis ④ Place and route ⑤ Verification ⑥ Tape-out ⑦ Masks, production ⑧ Test prototypes Fix
Errors found at step 5 can be fixed on the computer (inner dashed line). Errors found after step 6 mean making masks again (outer dashed line). Left out: the detailed checks within each step, packaging and testing, and trying the design on an FPGA before production.

First, you decide what the chip must do (the spec). Next, you describe how the circuit behaves in a special language. Inside a chip, a timing signal arrives at a steady pace. Each time, data moves from one storage part to the next. A way of writing down these moves and the math done between them is called RTL.

Software then turns that description into a network of small circuits that handle 0s and 1s. It does this automatically. This step is called logic synthesis. Nobody draws the transistors one at a time.

The building blocks come from a library of parts that were designed and checked in advance. It holds small logic circuits such as AND, and circuits that store one bit. The parts all have the same height, so they can be laid in rows like bricks. These parts are called standard cells.

Next, you decide where each part sits on the chip and which paths the wires take (place and route). Then a computer checks in detail that the chip runs at the target speed and follows the factory's manufacturing rules (verification).

Handing the checked design data to the manufacturer is called tape-out. The manufacturer makes masks from the data and builds the circuits on wafers in its factory. "What Is a Semiconductor Foundry?" explains the model where one company designs and another makes the chip.

The first chips back from the factory are switched on and tested for real. If an error turns up now, some or all of the masks must be made again. That costs money and several months. So designers often load the circuit into an FPGA and run it before production.

Here is one example of how long this takes. Google says its first TPU took 15 months from design to running in its data centers. Google presents this as an unusually short schedule.

CPU vs GPU vs FPGA vs ASIC

The more a circuit is tailored to a job, the more efficient it is at that job. In exchange, you give up flexibility for other jobs and an easy start. The table below simplifies the differences between the four.

What you can change laterEfficiency at a fixed jobBest for
CPUThe programLowerDoing anything
GPUThe programHigh for many identical calculationsGraphics, AI, science
FPGAThe circuit itselfMediumSmall volumes, changing specs
ASICNothingHighestLarge volumes, fixed specs

CPUs, GPUs and FPGAs are all ready-made chips that you buy and use. What they do is decided later, by a program or a circuit setting. Only an ASIC has its job decided before the chip is made, and built into its circuit.

Chips in phones and similar devices also contain circuits focused on AI math. Such a circuit is called an NPU. Narrowing the use to gain efficiency is the same idea as an ASIC ("What Is an NPU?"). Why GPUs are used for AI is covered in "Why Are GPUs Used for AI?"

Real products combine these. A phone's main chip puts a CPU, GPU, NPU and video circuits together on one chip. This is called an SoC. An SoC designed only for a company's own products, like Apple's A series, is a kind of ASIC. An SoC sold to many device makers counts as an ASSP, explained next. A table of how these terms relate is in "ASIC vs FPGA vs SoC".

ASIC vs ASSP: dedicated chips sold to many companies

Some chips are made for a narrow use but are listed in catalogs and sold to many companies. These are called ASSPs. ASSP stands for Application-Specific Standard Product.

In the narrow sense, an ASIC is a chip made for one company or one product. An ASSP has a fixed use, but anyone can buy it off the shelf. Tomahawk 5, mentioned earlier, is a product that many equipment makers buy and use. By this split, it is closer to an ASSP.

In the industry, though, such products are often called "ASICs" too, in a broader sense. Tomahawk 5 is sometimes called a "switch ASIC." What the word covers depends on the person and the setting, so judge from context.

Sharing the cost of prototypes

If masks cost so much, can small companies and universities never try out an ASIC? In fact, there is a way to cut prototype costs. Many designs are placed side by side on one mask set and made together in one production run. This is called an MPW (multi-project wafer). Since everyone rides together, like passengers on a shared bus, it is also called a shuttle.

A dedicated mask set holds one design only, while an MPW lets several designs share one mask set Dedicated mask MPW (shared) A A A A A B C D E One design pays it all Five designs share the cost
Each large square shows the area drawn on one mask. A to E are designs from different companies or universities. Left: a production mask with only design A repeated. Right: a prototype mask with five designs side by side. Left out: the real layout and number of designs, and the fact that there is one mask per layer.

The participants split the cost of the masks and wafers according to the area they use. Each gets only a limited number of chips, too few for mass production. Even so, they can check that their circuit works in real silicon.

For example, TSMC has offered this service under the name CyberShuttle since 1998. In Japan, VDEC (VLSI Design and Education Center) was set up at the University of Tokyo in 1996. It has gathered design data from universities across the country and offered low-cost prototyping.

Note that mass production after a prototype needs your own mask set. An MPW lowers the cost of prototypes, not the cost of mass production.

Common myths

Myth: An ASIC is faster than a CPU or GPU at every task

In fact, it is fast only at the job chosen at design time. A Bitcoin-mining ASIC cannot play video or run a spreadsheet. Even within AI math, a chip has strengths and weaknesses. The first TPU, for example, was made for having trained AI produce answers, and was not used to train AI. People tend to overlook the "dedicated" part of "dedicated means fast," which causes the myth.

Myth: Only big companies with huge budgets can make ASICs

In fact, an MPW lets you share the cost of a prototype. Choosing an older manufacturing generation instead of the leading edge also makes masks far cheaper. University labs and startups make chips this way. Mass production, however, still needs your own mask set and large design costs. You still need to expect strong sales. The myth arises because the ASICs in the news are mostly big companies' leading-edge chips.

Myth: ASIC and FPGA are two names for much the same thing

In fact, an FPGA is a ready-made chip you buy, and you write the circuit into it later. An ASIC has its circuit built in at the factory, so it cannot change after it is made. People mix them up because the same circuit is often tried on an FPGA first and then made as an ASIC.

By the numbers

ItemFigure
First TPU vs CPUs and GPUs of the same period (around 2015), on trained-AI tasks (Google, 2017)15 to 30 times the performance, 30 to 80 times per watt
First TPU development time (design to deployment)15 months
Estimated cost of a mask set (SemiAnalysis, 2022)Over $1 million at 28 nm, over $10 million at 7 nm
Layers that need masks on a leading-edge chip (same source)More than 60
Data handled by Tomahawk 5 (2022)51.2 terabits per second
Efficiency of the video transcoding chip (Google, 2021 paper)20 to 33 times that of systems without dedicated chips
Start of TSMC's shared prototyping service1998

Mask costs are estimates that vary widely by source and contract. Treat them only as a rough order of magnitude. Also, "X nm" is the name of a manufacturing generation, not the length of any part of the chip ("What Does 2nm or 3nm Mean?").

Learn more

Read next

Articles in the series “How computers work”

  1. How Do Computers Use Binary? Calculating with 0 and 1
  2. What Is a CPU? What It Does Inside Your Computer and Phone
  3. Why Are GPUs Used for AI? Matrix Math and Memory Explained
  4. What Is an Operating System? What an OS Actually Does
  5. How Does CPU Cache Work? Hit Rate, Lines and Locality
  6. What Is an NPU? The AI Engine in Phones and PCs Explained
  7. What Is an FPGA? A Chip You Can Rewire After It's Made
  8. What Is an ASIC? Custom Chips vs CPUs and FPGAs Explained
  9. How Compilers Work: From Source Code to Machine Code
  10. What Is a Logic Gate? AND, OR, NOT and How Gates Compute
  11. What Is RISC-V? The Open Instruction Set Explained
  12. What Is an Algorithm? Search, Sorting and Big-O Explained
  13. What Is a Database? Tables, SQL and Indexes Explained
  14. What Is Git? Version Control Basics and Git vs GitHub

Questions on this topic: IC design flow and EDA

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