LSI design flow and EDA

What is it called to reflect small fixes found late in design or during manufacturing by partially modifying the existing layout, without redoing the whole design?

  1. ATape-out
  2. BFloorplan
  3. CECO (engineering change order)
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Answer: C. ECO (engineering change order)

An ECO reflects fixes such as small logic bugs or timing adjustments through local changes without redoing all of place and route. If spare cells are placed in advance, some fixes can be made by changing only the metal-layer masks, saving time and cost.

  • A. Tape-out is handing off manufacturing data.
  • B. Floorplanning decides the rough placement.
  • C. Correct. Fixes are reflected through local changes.
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  1. Which set correctly names cells with no logic function (or auxiliary ones) placed among standard cells to fill gaps, tie well potentials and suppress supply noise?
  2. What is the task called of circuit-simulating standard cell delay and power across various input transition times, load capacitances, voltages and temperatures and compiling the results into tables?
  3. In static timing analysis, what is the technique called that multiplies delays by factors to add margin for transistor and wire delays varying by location even within the same chip?
  4. Which analysis method, rather than combining worst-case values at corners, treats delay variation as probability distributions and computes the probability of meeting timing?
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