LSI design flow and EDA

Which technique confirms mathematically, without simulation, that a circuit's logic has not changed before and after logic synthesis?

  1. AFormal equivalence checking (formal verification)
  2. BDRC
  3. CDicing
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Answer: A. Formal equivalence checking (formal verification)

Formal equivalence checking exhaustively confirms by mathematical methods whether two circuits implement the same logic function. It requires no test patterns and guarantees equivalence for all input combinations, so it is used to check circuits before and after logic synthesis and place and route.

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