LSI design flow and EDA

Which approach prefabricates a common base (master) covered with transistors and designs and manufactures only the wiring layers for each product?

  1. AGate array
  2. BFull custom
  3. CPDK
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Answer: A. Gate array

In a gate array, layers up through the transistors are made in advance as a common master, and only the wiring masks are designed per product. Fewer masks and shorter development made it popular for low-volume, high-mix LSIs. Today it has largely given way to FPGAs, structured ASICs and the like.

  • A. Correct. Only the wiring layers are designed per product.
  • B. Full custom designs every layer.
  • C. A PDK is the set of design data provided by a foundry.
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  1. In verification using SystemVerilog, which standard methodology is used to build reusable test environments (testbenches)?
  2. In layout verification, which check looks for electrical connection errors, such as inputs left floating (connected to nothing) or supplies shorted together?
  3. Which technique describes properties a design must satisfy (for example, "respond within 3 cycles of a request") and has them checked automatically during simulation or by formal verification?
  4. In low-power design, which standard format describes the "power intent", such as power domains, power shutoff and level shifters, separately from the circuit description?
  5. What is the verification called that uses dedicated tools to check whether synchronizers are correctly inserted where signals pass between circuits running on different clocks?