LSI design flow and EDA

In static timing analysis, which timing violation occurs when a signal changes too soon after the clock edge, so a flip-flop cannot correctly hold the previous data?

  1. ASetup violation
  2. BHold violation
  3. CDRC violation
Show answer and explanation

Answer: B. Hold violation

A hold violation occurs when the data path is too short and data is not held for the required time after the clock edge. Lowering the clock frequency does not fix it, so delay buffers are inserted. When the path is too long and data arrives too late, it is a setup violation.

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More LSI design flow and EDA questions

  1. What is the set of design data, including design rules, device models and cell libraries, that a foundry provides to designers called?
  2. Which is the representative circuit simulator that calculates voltages and currents of transistor-level circuits in detail using device models?
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  4. Which low-power design technique stops the clock to unused circuit blocks to reduce wasted power?
  5. Which is an appropriate fix when static timing analysis finds a setup violation?