LSI design flow and EDA

In verification using SystemVerilog, which standard methodology is used to build reusable test environments (testbenches)?

  1. AOPC
  2. BCMP
  3. CUVM (Universal Verification Methodology)
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Answer: C. UVM (Universal Verification Methodology)

UVM is a standard methodology and class library for building SystemVerilog testbenches from components such as drivers, monitors and scoreboards. Components can be reused, and constrained-random stimulus and coverage collection are easy to incorporate.

  • A. OPC is optical proximity correction in lithography.
  • B. CMP is chemical mechanical polishing.
  • C. Correct. It is the standard methodology for building testbenches.
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More LSI design flow and EDA questions

  1. In layout verification, which check looks for electrical connection errors, such as inputs left floating (connected to nothing) or supplies shorted together?
  2. Which technique describes properties a design must satisfy (for example, "respond within 3 cycles of a request") and has them checked automatically during simulation or by formal verification?
  3. In low-power design, which standard format describes the "power intent", such as power domains, power shutoff and level shifters, separately from the circuit description?
  4. What is the verification called that uses dedicated tools to check whether synchronizers are correctly inserted where signals pass between circuits running on different clocks?
  5. What is it called to reflect small fixes found late in design or during manufacturing by partially modifying the existing layout, without redoing the whole design?