LSI design flow and EDA

Which correctly describes static timing analysis (STA)?

  1. AFabricating a prototype chip and measuring its operating speed
  2. BApplying many test patterns and checking operation by simulation
  3. CCalculating the delay of each path in the circuit without test patterns and verifying whether timing constraints are met
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Answer: C. Calculating the delay of each path in the circuit without test patterns and verifying whether timing constraints are met

STA adds up cell and wire delays for every signal path in the circuit and exhaustively checks whether timing constraints such as setup and hold times are met. Because it needs no test patterns and verifies quickly, it is central to timing verification of large LSIs.

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