LSI design flow and EDA

What is the main purpose of clock tree synthesis (CTS) in the place-and-route stage?

  1. ATo reduce variation (skew) in the time the clock signal reaches each flip-flop
  2. BTo raise the supply voltage
  3. CTo fix design rule violations in the layout
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Answer: A. To reduce variation (skew) in the time the clock signal reaches each flip-flop

Variation in when the clock reaches the many flip-flops on a chip causes timing violations. CTS distributes the clock through buffers arranged like a tree, reducing variation in arrival time at each flip-flop (skew).

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  2. In static timing analysis, which timing violation occurs when a signal changes too soon after the clock edge, so a flip-flop cannot correctly hold the previous data?
  3. What is the set of design data, including design rules, device models and cell libraries, that a foundry provides to designers called?
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