Enter the cross-section and length of an on-chip wire, the metal and the dielectric constant of the insulator to calculate the wire's resistance, capacitance and signal delay. You can see in numbers why doubling the length roughly quadruples the wire delay, and how low-k dielectrics and line spacing affect it.
Results
Resistance per µm
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Wire resistance Rw
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Capacitance per µm
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Wire capacitance Cw
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Share of coupling to neighbors
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Wire-only delay 0.38·Rw·Cw
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Delay with driver and load
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The blue line is the delay including driver and load, the green line the wire-only delay 0.38·Rw·Cw, and the red dot marks the current length. The wire-only delay grows with the square of the length.
Resistance is R = ρL/(W·T). Capacitance uses a parallel-plate approximation: 2ε·W/H to the layers above and below plus 2ε·T/S to the two neighbors (ε = k·ε0). Fringing fields around the top and sides of the line are not included, so real capacitance is higher. Delay is 0.69·Rdrv·(Cw + CL) + 0.38·Rw·Cw + 0.69·Rw·CL, an approximation of the time for a step input to reach 50% at the far end (the Elmore delay of a distributed RC line is 0.5·Rw·Cw). Resistivities are room-temperature bulk values; enter the increase in narrow lines with the multiplier. Inductance is ignored.
See it as a graph
Other inputs stay at their current values while the chosen input varies from 1/4 to 4 times its current value. The red dot is the current value.
Wire resistance and the size effect
Wire resistance is R = ρL/(W·T): proportional to length and inversely proportional to cross-section. With the default Cu (1.7 µΩ·cm), 50 nm width and 100 nm thickness, it is 3.4 Ω per µm, or 3.4 kΩ for 1 mm. Once the width approaches the electron mean free path (about 40 nm in Cu), scattering at surfaces and grain boundaries increases and the resistive barrier takes up more of the cross-section, so the effective resistivity exceeds the bulk value. A multiplier of 3 raises the resistance to 10.2 kΩ and the wire delay threefold to about 463 ps.
Wire capacitance and the dielectric constant
Wire capacitance splits into capacitance to the layers above and below and coupling to neighboring lines on the same layer. In a parallel-plate approximation it is ε(2W/H + 2T/S) per unit length. With the defaults, the vertical part 2W/H is 1 and the lateral part 2T/S is 4, so coupling to neighbors makes up 80% of the total of 0.12 fF per µm, or 120 fF for 1 mm. With SiO2 (k = 3.9) the capacitance rises about 1.44 times to 0.173 fF/µm. Because tighter spacing increases lateral capacitance, low-k dielectrics and air gaps became important.
Distributed RC delay and the square law
Because a wire's resistance and capacitance are spread along its length, the time for a step input to reach 50% is about 0.38·Rw·Cw, not the 0.69RC of a single lumped RC (the Elmore estimate is 0.5·Rw·Cw). With the defaults the wire-only delay is 154 ps, and 267 ps including a 1 kΩ driver and a 10 fF load. Since both Rw and Cw scale with length, the wire-only delay grows with the square of the length: at 2 mm it is four times larger, 618 ps, and the total is 837 ps.
Ways to reduce wire delay
Long wires are commonly split by inserting buffers called repeaters. Splitting the default 2 mm wire into two 1 mm sections driven by the same driver gives 267 ps × 2, about 535 ps, ignoring the repeater's own delay, which is shorter than 837 ps. Splitting shrinks the square-law term, so total delay becomes roughly proportional to length. Other remedies include routing long wires on thicker, wider upper metal layers, lowering capacitance with low-k dielectrics, and using metals such as Co or Ru whose resistivity rises less in very narrow lines.
Both wire resistance R and capacitance C scale with length, so RC delay scales with length squared—doubling length roughly quadruples delay. Inserting buffers (repeaters) to segment long wires makes delay nearly linear in length. Advanced chips contain hundreds of thousands to millions of repeaters, whose power is not negligible; routing long nets on thick upper-level wires serves the same goal.
Parallel-plate capacitance C = εS/d is inversely proportional to spacing d, so halving the spacing roughly doubles inter-wire capacitance. As pitches shrink, lateral coupling comes to dominate total capacitance, raising delay, power and crosstalk. Since capacitance also scales with permittivity ε, low-k dielectrics and air gaps are the countermeasures. Real wires also add fringing-field capacitance at their edges.
Resistance R = ρL/(W × T); with ρ = 2×10⁻⁸ Ω·m, L = 1×10⁻³ m and W × T = 1×10⁻¹⁴ m², R = 2000 Ω, about 2 kΩ. Even a 1 mm run has this much resistance at a 100 nm square cross-section, and with wire capacitance (about 0.2 pF per mm) the RC delay reaches hundreds of ps. Long routes therefore use thick upper-level wires or repeaters.
BBecause surface and grain-boundary scattering of electrons increase, and the high-resistance barrier layer takes up a larger share
CBecause copper turns into a semiconductor
Show answer and explanation
Answer: B. Because surface and grain-boundary scattering of electrons increase, and the high-resistance barrier layer takes up a larger share
When linewidths approach or fall below the electron mean free path (about 40 nm in copper), scattering at surfaces and grain boundaries rises and resistivity can reach several times the bulk value; narrow lines also have smaller grains, adding grain-boundary scattering. Meanwhile, barrier layers of fixed thickness occupy a growing share of the cross-section. Metals with shorter mean free paths—cobalt, ruthenium, molybdenum—are therefore being evaluated and introduced.
FAQ
How much does the delay grow if the wire length doubles?
The wire-only delay 0.38·Rw·Cw grows about four times, because both Rw and Cw are proportional to length. The term from the driver's output resistance grows only about linearly, so the total grows by a factor between 2 and 4. With the defaults, the 267 ps delay at 1 mm becomes 837 ps at 2 mm, about 3.1 times.
When should I use 0.38RC, 0.5RC or 0.69RC?
0.69RC (ln 2 × RC) is the 50% delay of a single lumped resistor and capacitor. For a wire with uniformly distributed resistance and capacitance, the same 50% delay is about 0.38RC. 0.5RC is the Elmore delay of a distributed RC line; it is simple to calculate and widely used for estimates, but it is larger than the 50% delay.
Why is real wire capacitance larger than this tool's value?
This tool uses a parallel-plate approximation and leaves out the fringing fields that wrap around the top and sides of the line. When the width or spacing is comparable to or smaller than the thickness, this part is significant. Real designs get capacitance from parasitic extraction tools based on field solutions of the wire cross-section. About 0.2 fF per µm is a commonly used rule of thumb.