LSI design flow and EDA

What is the task called of circuit-simulating standard cell delay and power across various input transition times, load capacitances, voltages and temperatures and compiling the results into tables?

  1. ATape-out
  2. BDicing
  3. CLibrary characterization
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Answer: C. Library characterization

Characterization simulates each cell's delay and power for combinations of input transition speeds and output load capacitances and compiles them into tables (such as in Liberty format). Logic synthesis and static timing analysis use these tables to compute delays of large circuits quickly.

  • A. Tape-out is handing off manufacturing data.
  • B. Dicing separates the wafer into chips.
  • C. Correct. It measures cell characteristics and tabulates them.
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More LSI design flow and EDA questions

  1. In static timing analysis, what is the technique called that multiplies delays by factors to add margin for transistor and wire delays varying by location even within the same chip?
  2. Which analysis method, rather than combining worst-case values at corners, treats delay variation as probability distributions and computes the probability of meeting timing?
  3. In timing constraints (SDC), which setting specifies margin subtracted from the clock period to allow for expected clock jitter, skew and the like?
  4. In static timing analysis, what is the technique called that recalculates violating paths in detail based on how signals actually propagate, removing excess pessimism from ordinary analysis?
  5. In analog circuit design, which technique repeatedly simulates with randomly applied transistor variations from manufacturing to estimate performance distributions and yield?