LSI design flow and EDA

Which correctly describes logic synthesis?

  1. AThe step of placing cells on the chip and routing wires
  2. BThe step of converting an RTL description into a netlist made of gates from a cell library
  3. CThe step of transferring circuit patterns onto a wafer
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Answer: B. The step of converting an RTL description into a netlist made of gates from a cell library

Logic synthesis converts a behavioral description of a circuit written in RTL into connection information (a netlist) of logic gates and flip-flops from a cell library. Given constraints on area, speed and power, the tool optimizes the circuit to meet them.

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More LSI design flow and EDA questions

  1. Which correctly describes static timing analysis (STA)?
  2. Which hardware description languages are mainly used in RTL design?
  3. Which correctly describes DRC (design rule check) in layout verification?
  4. Which technique confirms mathematically, without simulation, that a circuit's logic has not changed before and after logic synthesis?
  5. Which correctly describes standard-cell design?