LSI design flow and EDA

Which set correctly names cells with no logic function (or auxiliary ones) placed among standard cells to fill gaps, tie well potentials and suppress supply noise?

  1. ASRAM, DRAM and flash
  2. BFiller cells, tap cells and decoupling capacitor cells
  3. CFlip-flops, adders and multipliers
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Answer: B. Filler cells, tap cells and decoupling capacitor cells

Filler cells fill gaps in cell rows to keep wells and power rails continuous, tap cells tie well and substrate potentials to prevent latch-up, and decoupling capacitor cells suppress supply noise with capacitance between power and ground. None has a logic function, but they are required in the layout.

  • A. These are types of memory.
  • B. Correct. They are auxiliary cells with no logic function.
  • C. These are cells and circuits with logic functions.
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More LSI design flow and EDA questions

  1. What is the task called of circuit-simulating standard cell delay and power across various input transition times, load capacitances, voltages and temperatures and compiling the results into tables?
  2. In static timing analysis, what is the technique called that multiplies delays by factors to add margin for transistor and wire delays varying by location even within the same chip?
  3. Which analysis method, rather than combining worst-case values at corners, treats delay variation as probability distributions and computes the probability of meeting timing?
  4. In timing constraints (SDC), which setting specifies margin subtracted from the clock period to allow for expected clock jitter, skew and the like?
  5. In static timing analysis, what is the technique called that recalculates violating paths in detail based on how signals actually propagate, removing excess pessimism from ordinary analysis?