LSI design flow and EDA

Which is an appropriate fix when static timing analysis finds a setup violation?

  1. AReduce delay by simplifying the logic on the path or switching to cells with higher drive strength
  2. BIncrease delay by adding delay buffers to the path
  3. CRaise the clock frequency
Show answer and explanation

Answer: A. Reduce delay by simplifying the logic on the path or switching to cells with higher drive strength

A setup violation occurs when the data path is long and data does not arrive before the next clock. Delay is reduced by cutting logic levels, switching to stronger cells, or placing cells closer to shorten wires. Lowering the clock frequency also resolves it. Increasing delay is the fix for hold violations.

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