LSI design flow and EDA

In static timing analysis, what is the technique called that multiplies delays by factors to add margin for transistor and wire delays varying by location even within the same chip?

  1. AOCV (on-chip variation) derating
  2. BClock gating
  3. CAntenna rules
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Answer: A. OCV (on-chip variation) derating

Even within one chip, threshold voltages, wire dimensions, supply voltage and temperature differ slightly by location, scattering delays. OCV applies separate factors to data and clock paths in setup and hold analysis to assume the worst combination. More precise methods such as AOCV and POCV, which account for path depth and distance, are also used.

  • A. Correct. It accounts for on-chip variation with factors.
  • B. Clock gating is a technique for reducing power.
  • C. Antenna rules are layout rules preventing gate damage during plasma processing.
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More LSI design flow and EDA questions

  1. Which analysis method, rather than combining worst-case values at corners, treats delay variation as probability distributions and computes the probability of meeting timing?
  2. In timing constraints (SDC), which setting specifies margin subtracted from the clock period to allow for expected clock jitter, skew and the like?
  3. In static timing analysis, what is the technique called that recalculates violating paths in detail based on how signals actually propagate, removing excess pessimism from ordinary analysis?
  4. In analog circuit design, which technique repeatedly simulates with randomly applied transistor variations from manufacturing to estimate performance distributions and yield?
  5. Which logic simulation method computes only the parts affected when a signal value changes (an event)?