LSI design flow and EDA

In timing constraints (SDC), which setting specifies margin subtracted from the clock period to allow for expected clock jitter, skew and the like?

  1. AClock uncertainty
  2. BDose
  3. CAspect ratio
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Answer: A. Clock uncertainty

Clock uncertainty is a setting that subtracts margin in timing analysis for effects such as clock jitter and the skew expected before place and route. Its value is adjusted by design stage, and after place and route the skew is replaced by values computed from the actual clock tree delays.

  • A. Correct. It is margin subtracted from the clock period.
  • B. Dose is the amount in ion implantation.
  • C. Aspect ratio is the ratio of depth to width.
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