LSI design flow and EDA

Which analysis method, rather than combining worst-case values at corners, treats delay variation as probability distributions and computes the probability of meeting timing?

  1. ADRC
  2. BLogic simulation
  3. CStatistical static timing analysis (SSTA)
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Answer: C. Statistical static timing analysis (SSTA)

Corner-based analysis assumes all variations are simultaneously at their worst, which can be overly pessimistic. SSTA treats each element's delay as a probability distribution and, accounting for correlations, computes the distribution of path delay to evaluate the probability of meeting timing more realistically.

  • A. DRC checks geometric rules in the layout.
  • B. Logic simulation checks circuit behavior for given inputs.
  • C. Correct. It is timing analysis treating variation as distributions.
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More LSI design flow and EDA questions

  1. In timing constraints (SDC), which setting specifies margin subtracted from the clock period to allow for expected clock jitter, skew and the like?
  2. In static timing analysis, what is the technique called that recalculates violating paths in detail based on how signals actually propagate, removing excess pessimism from ordinary analysis?
  3. In analog circuit design, which technique repeatedly simulates with randomly applied transistor variations from manufacturing to estimate performance distributions and yield?
  4. Which logic simulation method computes only the parts affected when a signal value changes (an event)?
  5. Which is the correct order of a typical digital LSI design flow?