LSI design flow and EDA

What is the step called that extracts wire resistance and capacitance from the layout after place and route?

  1. ALogic synthesis
  2. BATPG
  3. CParasitic extraction (RC extraction)
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Answer: C. Parasitic extraction (RC extraction)

Parasitic extraction calculates and extracts wire resistance and capacitance from the shapes and spacing of wires in the layout. These values are used to perform static timing analysis and power analysis accurately. It is a step growing in importance as wiring effects increase with scaling.

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  1. In verifying large SoCs, which technique runs the designed circuit on dedicated hardware or FPGAs and verifies it quickly together with software?
  2. What is it called to hand over the data for mask making to manufacturing after design and verification are complete?
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  4. Which design philosophy refines layouts and the like to make them less susceptible to manufacturing variation and defects?
  5. In analog layout, which technique splits paired transistors and places them so their centroids coincide?