LSI design flow and EDA

Which correctly describes DRC (design rule check) in layout verification?

  1. AVerifying that the connectivity of the schematic and the layout match
  2. BVerifying that the layout satisfies manufacturing rules such as minimum width and spacing
  3. CVerifying the logic function of the RTL by simulation
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Answer: B. Verifying that the layout satisfies manufacturing rules such as minimum width and spacing

DRC checks whether layout shapes violate design rules set by the manufacturing process, such as minimum width, spacing and overlap. Confirming that the connectivity of the schematic and layout match is called LVS (Layout Versus Schematic). Both are always performed before mask data is released.

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