LSI design flow and EDA

In layout verification, which check looks for electrical connection errors, such as inputs left floating (connected to nothing) or supplies shorted together?

  1. AERC (electrical rule check)
  2. BDRC
  3. COPC
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Answer: A. ERC (electrical rule check)

ERC (electrical rule check) detects violations of rules about electrical connectivity, such as floating inputs, outputs driving against each other, shorts between different supplies and unconnected well potentials. It is run at signoff alongside DRC, which checks geometric rules, and LVS, which checks agreement with the schematic.

  • A. Correct. It checks for electrical connection errors.
  • B. DRC checks geometric dimension and spacing rules.
  • C. OPC is an exposure correction, not a verification.
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More LSI design flow and EDA questions

  1. Which technique describes properties a design must satisfy (for example, "respond within 3 cycles of a request") and has them checked automatically during simulation or by formal verification?
  2. In low-power design, which standard format describes the "power intent", such as power domains, power shutoff and level shifters, separately from the circuit description?
  3. What is the verification called that uses dedicated tools to check whether synchronizers are correctly inserted where signals pass between circuits running on different clocks?
  4. What is it called to reflect small fixes found late in design or during manufacturing by partially modifying the existing layout, without redoing the whole design?
  5. Which set correctly names cells with no logic function (or auxiliary ones) placed among standard cells to fill gaps, tie well potentials and suppress supply noise?