VLSI and Hardware Interview Questions

When both inputs are 1

NAND is the negation of AND: its output is 0 only when all inputs are 1, and 1 otherwise. It is a universal gate from which NOT, AND and OR can be built, and in CMOS it takes just four transistors—fewer than AND, which is a NAND plus an inverter (six). Logic synthesis therefore builds circuits around NAND and NOR, and NAND flash is so named because its series-connected cells resemble a NAND structure.

3.5

The upper four bits, 0011, are the integer part, 3; the lower four bits, 1000, are the fraction, where the first bit weighs 2⁻¹ = 0.5. Together that is 3 + 0.5 = 3.5. Equivalently, reading the bits as the integer 56 and dividing by 2⁴ = 16 for the four fraction bits gives 56 ÷ 16 = 3.5. 56 ignores the binary point, and 3.8 misreads binary 1000 as the decimal ".8".

(NOT A) OR (NOT B)

De Morgan's theorem states NOT(A AND B) = (NOT A) OR (NOT B) and NOT(A OR B) = (NOT A) AND (NOT B): distributing a negation swaps AND and OR. In words, "not both true" equals "at least one false." In schematics a NAND can be redrawn as an OR with bubbled inputs, which helps when handling active-low signals or building circuits from NAND gates alone.

Sign, exponent and significand

A floating-point number represents a value as (−1)^sign × 1.significand × 2^exponent and stores three parts: a sign bit for positive or negative, an exponent field for the power of two, and a significand for the significant digits. Because the exponent moves the binary point, the same number of bits covers values from tiny to huge. Splitting into integer and fractional parts is the fixed-point idea, and parity is for error detection.

It captures the value of the D input at a clock edge and holds it until the next edge

A D flip-flop captures its D input on the rising (or falling) clock edge and holds it until the next edge; changes between edges do not affect the output. It is the building block of sequential circuits—CPU registers, pipeline stage boundaries and counters—and is internally two latches in a master-slave arrangement. Correct capture requires meeting setup and hold times.

11-bit exponent, 52-bit significand

Double precision (FP64) uses 1 sign bit, 11 exponent bits and 52 significand bits, 64 in total. The exponent bias is 1023, covering roughly 10⁻³⁰⁸ to 10³⁰⁸, and the 53 bits of precision including the implied 1 correspond to about 15–16 decimal digits. Both fields are wider than in single precision, and it is the standard for scientific computing. An 8-bit exponent keeps the single-precision width while widening only the significand, which is not a standard format.

When the two inputs are different

XOR outputs 1 when its two inputs differ and 0 when they match: A⊕B = A·¬B + ¬A·B. It can also be seen as "invert the other input if one input is 1, pass it unchanged if 0," making it a controlled inverter. It computes the sum in a half adder and is used in comparators (equality detection with XNOR), parity generation, stream ciphers and CRC calculation.

Precision increases by one bit for the same number of stored bits

Normalized in binary, every nonzero number has the form 1.xxx × 2^exponent, so the leading digit is always 1. There is no need to store a known 1, so it is omitted and the bit is used for the fraction instead. Single precision thus stores 23 significand bits but has 24 bits of precision. Subnormals, with an all-zero exponent, treat the leading digit as 0. Negative numbers use the sign bit, and rounding error does not disappear.

It increases

The gate behaves like a parallel-plate capacitor with Cox = ε/t per unit area. Thinning the dielectric raises capacitance, so the same gate voltage induces more channel charge, increasing drive current and suppressing short-channel effects. But once SiO2 reached about 1.2 nm, tunneling leakage hit its limit, and HfO2-based high-k dielectrics, which can be physically thicker, were introduced: at Intel from the 45 nm generation (2007), and at most other manufacturers from the 28–32 nm generations.

The gate surrounds the entire perimeter of the channel, such as nanosheets

A gate-all-around (GAA) transistor stacks several channels shaped as sheets a few nm thick (nanosheets) or wires, each fully surrounded by the gate. Control from all sides is even stronger than in a FinFET, suppressing short-channel effects down to shorter gate lengths. Samsung adopted it at 3 nm (2022), TSMC at 2 nm and Intel at 18A, making it the successor standard to the FinFET.

The mobility of electrons in the channel is higher than that of holes

Electrons carry current in an nMOS and holes in a pMOS, and in silicon inversion layers electron mobility is about 2–3 times hole mobility, so an nMOS of the same size drives more current. CMOS balances this by widening the pMOS. In advanced processes, compressive strain from SiGe boosts pMOS mobility, and in FinFETs the fin sidewalls are (110) planes, which favor holes, so the gap has narrowed considerably.

Shortening the gate lowers the threshold voltage and increases off-state leakage

As gate length shrinks, the source and drain depletion regions become relatively large and control part of the channel charge instead of the gate. Consequences include threshold roll-off, drain-induced barrier lowering (DIBL), degraded subthreshold swing and rising off-state leakage. Device characteristics also become highly sensitive to small process variations in gate length.

It rises

Reverse-biasing the source-to-body junction widens the depletion region under the gate and increases its charge, so a larger gate voltage is needed to compensate—the threshold voltage rises (the body effect). In stacked transistors the upper devices see raised source potentials, so their Vth increases and they slow down. Conversely, adjusting body voltage to tune Vth is used to cut leakage.

A material with a high dielectric constant gives large gate capacitance with a thicker physical film, suppressing tunneling current

Below about 1.2 nm, SiO2 gate leakage from tunneling multiplies several-fold with every 0.1 nm of thinning. Hafnium-based oxides with relative permittivity of about 20–25 allow several times the physical thickness at the same capacitance, cutting leakage by orders of magnitude. Because high-k films pin the threshold with polysilicon gates (Fermi-level pinning), they are paired with metal gates, in use since the 45 nm generation (2007).

A channel exists even at a gate voltage of 0 V, so current flows

A depletion-mode MOSFET has a built-in channel and conducts even at 0 V gate voltage (normally on). For an n-channel device, a negative gate voltage removes the channel and stops the current. Early NMOS logic used them as load devices. Because they conduct when power is lost, they require safety considerations; GaN HEMTs are also inherently normally on, so special structures are used to make them normally off.

To increase carrier mobility and drive current

Straining silicon alters its band structure, reducing effective mass and scattering to boost mobility. Tensile strain along the current direction helps nMOS, compressive strain helps pMOS; methods include embedding SiGe in pMOS source/drain regions and capping nMOS with tensile nitride films. Introduced around the 90 nm generation (2003), strain became a pillar of performance improvement alongside scaling.

0.3 ns

Setup slack is calculated as "required time − arrival time." The data arrival time is 0.2 + 1.4 = 1.6 ns and the required time is the next clock edge minus the setup time, 2.0 − 0.1 = 1.9 ns, so the slack is 1.9 − 1.6 = 0.3 ns. Being positive, it meets the constraint. 0.4 ns is the value obtained by forgetting to subtract the setup time, and 0.5 ns by adding the setup time instead. A negative slack means a violation.

400 MHz

The minimum clock period is the sum of the clock-to-output delay, the combinational logic delay and the setup time. 0.15 + 2.2 + 0.15 = 2.5 ns, so the maximum frequency is 1 ÷ 2.5 ns = 400 MHz. About 425 MHz comes from 2.35 ns, which leaves out the setup time, and about 455 MHz from the 2.2 ns combinational logic delay alone. The maximum frequency of the whole chip is set by the tightest of such paths, the critical path.

WNS is the worst slack value and TNS is the sum of the negative slacks

WNS (Worst Negative Slack) is the worst slack among all paths and indicates how far the frequency can be raised. TNS (Total Negative Slack) is the sum of the negative slacks of the violating path endpoints. For example, with three endpoints at −0.1 ns, WNS is −0.1 ns and TNS is −0.3 ns. Even if the magnitude of WNS is small, a large TNS magnitude means many paths need fixing. The number of violations is reported by a separate metric, and WNS and TNS are computed for setup and for hold separately.

+0.02 ns

When the capture clock arrives late (positive skew), the capturing edge shifts later, giving more time for setup. The required time is 1.0 + 0.05 − 0.08 = 0.97 ns and the arrival time is 0.1 + 0.85 = 0.95 ns, so the slack is +0.02 ns. −0.03 ns ignores the skew, and −0.08 ns treats the skew in the opposite direction (as if the capture clock arrived early). Note that the same skew works against hold.

Setup gains margin and hold becomes tighter

Setup concerns capture at the next edge, so the later the capture edge, the longer the data arrival can be waited for. Hold checks that new data launched by the same edge does not overwrite the previous data, so the later the capture edge, the greater the risk that the new data arrives too early. For example, with a skew of +0.1 ns, setup slack increases by 0.1 ns and hold slack decreases by 0.1 ns. Negative skew has the opposite effect.

−0.05 ns (violated)

Hold slack is "arrival time − required time" and checks whether data arrives too early. The minimum data arrival time is 0.08 + 0.02 = 0.10 ns and the required time is the capture clock arrival of 0.1 ns plus the 0.05 ns hold time, 0.15 ns, so the slack is 0.10 − 0.15 = −0.05 ns, a violation. +0.05 ns ignores the skew, and +0.15 ns adds the skew in the favorable direction. This violation is common on paths with little logic in between, such as shift registers.

The hold check does not depend on the clock period, so the violation remains

The hold check looks at whether new data launched by the same clock edge corrupts the previous data at the capturing side, and on such paths the clock period does not appear in the equation. Lowering the frequency therefore leaves the −0.03 ns slack unchanged, without making it worse either. Setup, by contrast, depends on the period, so lowering the frequency can rescue it. A hold violation found after manufacturing tends to be a fatal defect that cannot be fixed by adjusting the frequency, so it is important to fix it reliably at the design stage.

That the added delay does not leave the same path short of setup slack

A hold violation means the data arrives too early, so delay is added to the data path to make it arrive later. However, the added delay also delays the arrival time for setup. A buffer that improves hold by 0.05 ns at the fast corner can add 0.1 ns or more of delay at the slow corner, so buffers must be inserted only within the available setup margin. Adding the same delay to the capture clock cancels out the improvement, and raising the drive strength to reduce delay defeats the purpose.

An HDL description represents circuits that operate concurrently

An HDL looks like a program, but logic synthesis turns what is written into gates and flip-flops. Every part of a circuit operates at all times, so multiple assign statements and always blocks work in parallel regardless of their order in the text. Thinking "do this, then that" as in software leads to unintended circuits, so it is important to picture the circuit being created while writing.

To define a circuit component with input and output ports so it can be used inside other modules

A module defines a block of circuitry with input and output ports, representing anything from an adder or counter to an entire CPU. A defined module can be used as a component any number of times inside other modules (instantiation), with its ports wired together to build larger circuits. Circuits are built hierarchically, much like placing and wiring parts on a board.

wire represents connections driven by assign statements and the like; reg is a signal assigned inside always blocks, but a reg does not necessarily become a flip-flop

In Verilog, signals driven by assign statements or module outputs are declared wire, and signals assigned inside always blocks are declared reg. reg looks like short for register, but assigned inside always @(*) it becomes combinational logic, not a flip-flop. Whether a flip-flop results depends on whether the value is updated on a clock edge. SystemVerilog allows both to be written as logic.

All right-hand sides at that time step are evaluated first, and then the left-hand sides are updated together

With nonblocking assignment, at the clock edge every <= right-hand side is first evaluated using the old values, and only then are all left-hand sides updated together. This mirrors real hardware, where many flip-flops on the same clock capture their pre-edge inputs simultaneously. That is why nonblocking assignment is the rule for describing clocked sequential logic.

Use nonblocking (<=) for clocked sequential logic and blocking (=) in combinational always blocks

Writing sequential logic with nonblocking assignments matches hardware where all flip-flops capture values simultaneously, so results do not depend on statement order or on the execution order of other always blocks. Combinational logic naturally computes intermediate values from top to bottom, so blocking assignments are used there. It is also important not to mix the two within one always block.

It runs whenever any signal read inside the block changes, describing combinational logic

The list inside @( ) after always is called the sensitivity list and specifies which signal changes trigger the block. Writing "*" automatically includes every signal read in the block, correctly describing combinational logic. Listing signals by hand invites omissions, so "@(*)" or SystemVerilog's always_comb is the safe choice for combinational logic.

Assign default values to every output signal at the top of the block before the conditional logic

Putting defaults such as "y = 0; valid = 0;" at the top ensures every output is assigned at least its default on whatever path the later branches take, so nothing needs to hold its value and no latch forms. This is especially helpful for state machine outputs with many conditions. With SystemVerilog's always_comb, tools also warn if a latch is inferred.

A delay specification such as #10

"#10" advances simulation time by 10 units, but logic synthesis cannot build delays, so it ignores them. Real circuit delays are set by the gates and wiring used. Testbench constructs such as $display and file I/O likewise do not become hardware. Mixing such constructs into synthesizable RTL causes simulation and hardware behavior to diverge.

To keep frequently used data close to the CPU and bridge the speed gap with main memory

While a CPU clock lasts 0.2–0.3 ns, a DRAM access takes tens to 100 ns—hundreds of cycles. Frequently used data and instructions are therefore kept in fast SRAM caches to cut waiting. Caches exploit temporal locality (reusing the same data soon) and spatial locality (using nearby addresses next), with L1 reachable in a few cycles and even L3 in tens of cycles.

Updating the same sum variable many times inside a loop

Temporal locality is the tendency to reuse data soon after using it, and a variable read and written repeatedly inside a loop is the classic example. Such data is reused while still in the cache or registers, so accesses are fast. Reading an array from start to end is an example of spatial locality, using nearby addresses in succession, which is a different property. Reading random addresses once each has almost no locality of either kind.

Programs (instructions) and data are stored in the same main memory, and instructions are read and executed in order

In the von Neumann (stored-program) architecture, instructions and data share main memory and the CPU fetches and executes instructions in sequence. Treating programs as modifiable data gives it flexibility, and it underlies modern computers. Because instructions and data compete for the same path, however, speed is constrained—the von Neumann bottleneck—so most CPUs split their L1 caches into instruction and data caches (a Harvard-style idea).

17 bits

A 64-byte line = 2⁶, so the offset is 6 bits. The number of lines is 32 KB ÷ 64 B = 32,768 ÷ 64 = 512 = 2⁹, and in a direct-mapped cache each line is its own set, so the index is 9 bits. The rest is the tag: 32 − 9 − 6 = 17 bits. 19 bits would apply to a 4-way set-associative cache, where the index shrinks by 2 bits, not to a direct-mapped one.

To increase performance per watt through parallel processing

Dynamic power scales with voltage squared and frequency, so by the mid-2000s ever-higher clocks hit thermal limits (around 100 W). The industry instead placed multiple cores within the same power budget and divided the work among them. Two cores at a slightly lower frequency deliver much better performance per watt. To benefit, however, software must split its work into parallel tasks.

0 bits

In a fully associative cache any data can go anywhere, so the whole cache is a single set. No set needs to be selected, so the index is 0 bits; the address splits into just offset and tag, and every access compares against all tags. That requires many comparators, so it does not suit large caches and is used for small structures such as TLBs. The line size determines the offset width, not the index.

It limits instructions to a small number of simple ones, making pipelining easier

RISC limits instructions to simple, uniform-length operations, performs arithmetic only between registers and restricts memory access to load/store instructions. Uniform execution times suit pipelining; ARM and RISC-V are leading examples. CISC designs such as x86 now decode their complex instructions into simple internal micro-ops, so the practical gap has narrowed.

2.5 ns

The L1 miss penalty is the L2 average access time, 10 + 0.2 × 100 = 30 ns. The average memory access time is therefore 1 + 0.05 × 30 = 1 + 1.5 = 2.5 ns. 2.0 ns forgets the 10 ns L2 hit time, computing 1 + 0.05 × (0.2 × 100). 6.0 ns multiplies the 100 ns memory time directly by the L1 miss rate, ignoring the L2.

Because the charge stored in the capacitor is gradually lost through leakage current

Charge on the capacitor gradually leaks away through the cell transistor's subthreshold and junction leakage. Refresh reads and rewrites each cell before its data becomes unreadable; every row must be refreshed within 64 ms up to DDR4, and within 32 ms in DDR5. During refresh, the bank cannot be accessed and power is consumed, a burden that grows with capacity. A limit on write cycles is a characteristic of flash memory.

Two cross-coupled inverters and two access transistors

A 6T SRAM cell combines a latch of two cross-coupled inverters (four transistors), each feeding the other's input, with two access transistors connecting it to the bit lines. Positive feedback holds its state, so no refresh is needed while powered. At about 120–150F² it is roughly 20 times larger than a DRAM cell, but it is built in the same process as logic and is fast, making it the workhorse of CPU caches.

Reading changes the cell's charge, so the data is amplified by a sense amplifier and written back to the cell

Connecting the cell capacitor to the bit line shares its charge with the bit line's large parasitic capacitance, destroying the original state (destructive read). The sense amplifier therefore amplifies a difference of tens to about a hundred mV to decide 0 or 1 and simultaneously writes the amplified level back into the cell. Because this write-back effectively refreshes the cell, refresh is performed simply by activating and closing a row.

TLC

By bits per cell, flash is SLC (1 bit), MLC (2), TLC (3) or QLC (4). TLC distinguishes eight threshold-voltage states and stores three times as much as SLC in the same cells. More bits lower cost but narrow the gaps between states, hurting endurance, speed and retention. TLC dominates mainstream SSDs today, with QLC growing for high-capacity drives.

Trench and stacked

To keep around 10 fF of capacitance as cells shrink, DRAM has made its capacitors three-dimensional: trench capacitors dug deep into the substrate, and stacked capacitors built as tall cylinders above the transistor. Stacked capacitors now dominate. In advanced parts they are tens of nm wide yet over 1 µm tall—aspect ratios of several tens—and supporting films keep them from toppling. Floating gates and charge traps are flash structures.

Electrons are moved into or out of a floating gate or charge-trap layer, changing the transistor's threshold voltage

A flash cell is a transistor with a floating gate (or charge-trap layer) beneath its control gate that stores electrons. Moving electrons in or out with high voltage—by tunneling, for example—shifts the threshold voltage, which distinguishes 0 from 1. Surrounded by insulating films a few nm thick, the electrons are retained for about ten years without power. Reading applies a set gate voltage and checks whether current flows.

It is volatile memory that loses data when the power is turned off

DRAM stores data as charge and is volatile: when power is removed, the charge is not maintained and the data is lost. Unlike SRAM, also volatile, it needs refresh even while powered. Chilled right after power-off, however, DRAM can retain data for seconds to minutes—exploited by the "cold boot attack" to read encryption keys from memory. Flash memory and similar devices are non-volatile.

Memory cells are stacked vertically in many layers to increase capacity

As planar scaling neared its limit around 15 nm, 3D NAND, which stacks cells vertically, entered mass production around 2013 and became mainstream. Deep cylindrical channel holes are etched through a thick stack of alternating conductive and insulating layers, and cells are formed on the hole walls. Capacity grows without shrinking cells aggressively, and interference drops. Three bits per cell is TLC, commonly combined with 3D NAND.

Specification → RTL design → logic synthesis → place and route

Specification design first fixes functions and performance; RTL is then written in a hardware description language such as Verilog or VHDL. Logic synthesis converts it into a gate-level netlist, and place-and-route produces the chip layout. Verification occurs at every stage, and the result is output as mask data. Because the flow moves from abstract descriptions to concrete geometry, no other order works. For leading-edge chips, specification to tape-out can take one to two years.

The step of converting an RTL description into a netlist made of gates from a cell library

Logic synthesis converts RTL behavioral descriptions into a netlist of logic gates and flip-flops from the cell library. Given timing, area and power constraints, the tool simplifies logic and selects cells of suitable drive strength to meet them. Placing cells and routing wires is place-and-route, and transferring patterns to wafers is lithography.

Calculating the delay of each path in the circuit without test patterns and verifying whether timing constraints are met

STA sums cell and wire delays along every signal path and exhaustively checks timing constraints such as setup and hold times. It needs no test patterns and covers paths that patterns might miss, so it is central to timing verification of large ICs. It does not check logical correctness, however, so functionality is verified separately by simulation and other means.

Verilog HDL and VHDL

RTL design uses hardware description languages such as Verilog HDL (and its extension SystemVerilog) or VHDL to describe how data flows between registers each clock cycle. Unlike software languages, the described operations run concurrently as hardware. HTML describes web pages and SQL queries databases; neither can describe circuits.

Verifying that the layout satisfies manufacturing rules such as minimum width and spacing

DRC checks whether layout shapes violate design rules derived from manufacturing, such as minimum width, spacing, overlap and density. Advanced processes have thousands of rules, verified automatically by tools. Checking that layout connectivity matches the schematic is LVS (layout versus schematic), and checking logic function is simulation. DRC and LVS are always run before mask data is released.

Formal equivalence checking (formal verification)

Formal equivalence checking mathematically and exhaustively verifies that two circuits implement the same logic function. It needs no test patterns and guarantees equivalence for all input combinations, so it is used before and after synthesis, place-and-route and ECOs. Exhaustive simulation is impractical once inputs reach just a few dozen bits. DRC checks layout geometry rules.

Cells such as gates, designed and verified in advance, are placed and wired to build the circuit

In standard-cell design, basic circuits such as NAND gates and flip-flops are pre-designed and verified as cells of uniform height, and synthesis and place-and-route tools arrange them in rows and connect them. The uniform height lets cells share power rails and makes automation easy. Most large digital ICs use this approach. Designing everything by hand is full custom, and reprogramming after manufacture describes FPGAs.

Users can rewrite the configuration of the logic circuit after manufacturing

An FPGA consists of logic blocks with small lookup tables (LUTs) and programmable interconnect whose configuration can be rewritten after manufacture. With no fabrication lead time or mask costs, unlike an ASIC, it suits prototypes, low volumes and equipment needing updates. Its reconfiguration circuitry adds overhead, so the same function in an ASIC is faster, lower power and smaller. It is not an analog-only device.

Before dicing, probes contact each chip on the wafer to test its electrical characteristics

In wafer test, a prober moves the wafer so that probe-card needles touch each chip's pads, and a tester checks electrical characteristics and function. Catching bad chips at this stage avoids wasting package materials and assembly effort, since defects cost more the later they are found. Testing after encapsulation is final test, and running products long-term to measure failure rates is reliability testing.

To apply stresses such as high temperature and voltage to remove products prone to early failure before shipment

Burn-in operates products for hours to tens of hours at around 125 °C and above-nominal voltage, forcing latent defects to fail early so those parts can be screened out. The aim is to get through the infant-mortality portion of the bathtub curve before shipment, and it is applied to high-reliability products such as automotive and server parts. It differs in purpose from visual inspection or film-thickness measurement.

Connecting the flip-flops in a circuit like a shift register to make it easy to set and observe internal states

Scan design adds a multiplexer at each flip-flop input; in test mode the flip-flops are chained into scan chains so arbitrary values can be shifted in and internal values shifted out. This turns sequential-circuit testing into combinational-circuit testing, letting ATPG automatically generate patterns with high fault coverage. It has nothing to do with microscope scanning or voltage sweeps.

Leakage current and voltage levels of I/O pins, and supply current

DC test measures whether static electrical characteristics meet spec: I/O leakage, output high and low voltage levels, input thresholds, and standby and operating supply current. It usually begins with a contact test that drives current through each pin's protection diode to confirm probe contact and detect opens or shorts. Logic function is checked by functional test and appearance by visual inspection.

Test circuitry is built into the chip so that the chip tests itself

BIST builds pattern-generation and result-checking circuits into the chip so it can test itself. Memory BIST generates patterns such as March tests at speed, while logic BIST uses pseudo-random patterns. It reduces dependence on expensive testers and test time, and in automotive chips it enables self-diagnosis in the field, for example at every power-up.

A fixture that contacts needles to the chip electrodes on a wafer and connects them electrically to the tester

A probe card is a product-specific fixture with many needles arranged to match the chip's pad layout. The prober aligns the wafer by camera and raises the chuck to bring pads into contact with the needles, electrically connecting tester and chip. Needle types include angled cantilever, vertical and MEMS-fabricated probes. It is unrelated to molds for encapsulation or wafer carriers.

A fault in which a signal line's value is fixed at 0 or 1

The stuck-at model assumes a signal line is permanently fixed at 0 (stuck-at-0) or 1 (stuck-at-1), giving 2n faults for n lines. Simple as it is, it represents many physical defects such as shorts and opens, and it underpins ATPG and fault-coverage evaluation. Slow signals are handled by delay fault models, and temperature rise is not a fault model.

The fraction of modeled faults that the test can detect

Fault coverage is the fraction of modeled faults that the test patterns detect. The escaping defect level is estimated as DL = 1 − Y^(1−T) for yield Y and coverage T; even with Y = 0.5 and T = 99%, DL is about 0.7% (about 7,000 DPPM). Automotive products therefore demand coverage well above 99%. It is distinct from the shipped defect rate or yield itself.

Input impedance: infinite; output impedance: 0

An ideal op-amp is assumed to have infinite input impedance (no current into the inputs), zero output impedance (output voltage independent of load) and infinite open-loop gain. From these assumptions, a negative-feedback circuit keeps both inputs at the same voltage—the "virtual short"—so circuit gain depends only on resistor ratios. Real op-amps have open-loop gains of about 10⁵–10⁶, which fall with frequency.

About 160 Hz

An RC filter's cutoff is fc = 1/(2πRC); with RC = 1×10³ × 1×10⁻⁶ = 1 ms, fc ≈ 159 Hz, about 160 Hz. At this frequency the output is −3 dB (about 0.707×) with a 45° phase lag, and above it the response falls 20 dB per decade. Because first-order roll-off is gentle, second- or higher-order active filters using op-amps are used for sharper cutoff.

+10

A non-inverting amplifier's gain is 1 + R2/R1 = 1 + 90/10 = 10, with the output in phase with the input. Since the input goes straight into the non-inverting terminal, the input impedance is very high and does not load the source. Its gain cannot be less than 1 (R2 = 0 gives a voltage follower). Don't confuse it with the inverting gain −R2/R1 (−9 here).

Its voltage gain is 1, with high input impedance and low output impedance, so it is used as a buffer

A voltage follower is a non-inverting amplifier with the output tied directly to the inverting input (gain 1), so the output equals the input. Its very high input impedance and low output impedance make it a buffer that passes signals from high-impedance sensors or dividers to later stages or loads without altering them. As this is the deepest-feedback configuration, some op-amps lack phase margin and may oscillate, so check that the datasheet says "unity-gain stable."

Gain is reduced, but gain stability improves, bandwidth widens and distortion decreases

Negative feedback subtracts part of the output from the input, reducing gain. In return, closed-loop gain becomes about 1/β (the inverse of the feedback fraction), largely independent of device variation and temperature; bandwidth widens; and distortion and output impedance shrink by a factor of (1 + loop gain). Op-amp circuits are built on this. At frequencies where the phase shifts enough to make feedback positive, however, the loop oscillates, so phase margin must be secured.

It is good at rejecting noise that appears equally on both inputs (common-mode signals)

A differential amplifier ideally amplifies the difference between its inputs while rejecting components common to both (common-mode signals). CMRR is the ratio of differential to common-mode gain, typically 80–120 dB for op-amps. Higher CMRR means better immunity to common-mode noise such as pickup on long cables or supply fluctuations. CMRR falls at higher frequencies and is degraded by mismatched external resistors, so instrumentation amplifiers are used when precision matters.

40 dB

Voltage gain in decibels is 20 log₁₀(gain): 20 × log₁₀100 = 40 dB. Handy values: 10× is 20 dB, 2× is about 6 dB, and √2× about 3 dB. Power is proportional to voltage squared, so power uses 10 log₁₀, making a 100× power gain 20 dB. Decibels let cascaded gains be added rather than multiplied and make wide ranges of values easier to handle.

Integrator

With a resistor R at the input and a capacitor C in feedback, the input current Vin/R charges C, so Vout = −(1/RC)∫Vin dt—proportional to the time integral of the input. Its gain falls 20 dB per decade, a low-pass response. At DC, the op-amp's offset is also integrated until the output saturates, so practical circuits add a large resistor across C. Integrators are used in waveform shaping, filters, dual-slope ADCs and the integral term of PID control.