Memory Hierarchy

In a fully associative cache, how many address bits are used for the index (the part that selects a set)?

  1. A6 bits, determined by the line size
  2. BAs many bits as there are lines
  3. C0 bits
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Answer: C. 0 bits

In a fully associative cache any data can go anywhere, so the whole cache is a single set. No set needs to be selected, so the index is 0 bits; the address splits into just offset and tag, and every access compares against all tags. That requires many comparators, so it does not suit large caches and is used for small structures such as TLBs. The line size determines the offset width, not the index.

  • A. The line size determines the number of offset bits.
  • B. Index bits scaled to the line count apply to direct-mapped caches.
  • C. Correct. With only one set, no index is needed.
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More Memory Hierarchy questions

  1. With an L1 hit time of 1 ns and miss rate of 5%, an L2 hit time of 10 ns and local miss rate of 20%, and main memory access time of 100 ns, what is the average memory access time?
  2. In a direct-mapped cache, elements of two arrays map to the same cache location and evict each other on every alternating access. How is this miss classified?
  3. Which method is effective at reducing the cache misses that occur when a program accesses data for the first time?
  4. Which misses are not reduced even by making a cache fully associative?
  5. What is the effect of increasing a cache's line size?