Memory Hierarchy

For a direct-mapped cache with 32-bit addresses, 32 KB capacity and 64-byte lines, how many tag bits are there?

  1. A15 bits
  2. B19 bits
  3. C17 bits
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Answer: C. 17 bits

A 64-byte line = 2⁶, so the offset is 6 bits. The number of lines is 32 KB ÷ 64 B = 32,768 ÷ 64 = 512 = 2⁹, and in a direct-mapped cache each line is its own set, so the index is 9 bits. The rest is the tag: 32 − 9 − 6 = 17 bits. 19 bits would apply to a 4-way set-associative cache, where the index shrinks by 2 bits, not to a direct-mapped one.

  • A. 15 bits results from mistaking the index for 11 bits.
  • B. 19 bits applies if it were 4-way, with a quarter as many sets.
  • C. Correct. 32 − 9 (index) − 6 (offset) = 17 bits.
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More Memory Hierarchy questions

  1. How many sets does a 4-way set-associative cache with 32-bit addresses, 32 KB capacity and 64-byte lines have?
  2. In a fully associative cache, how many address bits are used for the index (the part that selects a set)?
  3. With an L1 hit time of 1 ns and miss rate of 5%, an L2 hit time of 10 ns and local miss rate of 20%, and main memory access time of 100 ns, what is the average memory access time?
  4. In a direct-mapped cache, elements of two arrays map to the same cache location and evict each other on every alternating access. How is this miss classified?
  5. Which method is effective at reducing the cache misses that occur when a program accesses data for the first time?