PCIe 3.0 vs 4.0 vs 5.0 vs 6.0: Speed and Differences

PCI Express doubles its per-lane transfer rate with each generation, so a link of the same width gets twice the bandwidth: 3.0 runs at 8 GT/s, 4.0 at 16 GT/s, 5.0 at 32 GT/s and 6.0 at 64 GT/s. Generations 3 to 5 use simple two-level signaling, while 6.0 switches to four-level PAM4 with forward error correction. Every generation is backward and forward compatible, so a device simply runs at the highest speed that both sides support.

AspectPCIe 3.0PCIe 4.0PCIe 5.0PCIe 6.0
Introduced2010201720192022 (specification)
Transfer rate per lane8 GT/s16 GT/s32 GT/s64 GT/s
Signaling and encodingNRZ, 128b/130bNRZ, 128b/130bNRZ, 128b/130bPAM4 with forward error correction and fixed-size FLIT packets
Bandwidth per lane (one direction)About 1 GB/sAbout 2 GB/sAbout 4 GB/sAbout 7.5 GB/s
x4 link (one direction)About 4 GB/sAbout 8 GB/sAbout 16 GB/sAbout 30 GB/s
x16 link (one direction)About 16 GB/sAbout 32 GB/sAbout 63 GB/sAbout 121 GB/s
Typical devicesOlder NVMe SSDs and graphics cardsCurrent graphics cards and NVMe SSDs (about 7 GB/s)Newest NVMe SSDs (up to about 14 GB/s) and high-end graphics cardsData-center accelerators, high-speed networking and AI systems

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

PCIe 3.0
Still adequate for most graphics cards and for everyday SSD use.
PCIe 4.0
The mainstream today for fast NVMe SSDs and graphics cards.
PCIe 5.0
For the fastest SSDs and the most demanding devices, where bandwidth is the limit.
PCIe 6.0
For servers and AI infrastructure, where very high bandwidth per link is needed.

FAQ

Does each PCIe generation double the speed?

Yes. 3.0 runs at 8 GT/s, 4.0 at 16 GT/s, 5.0 at 32 GT/s and 6.0 at 64 GT/s per lane, so the same link width gets twice the bandwidth.

Can I put a PCIe 4.0 card in a PCIe 3.0 slot?

Yes. PCIe is backward and forward compatible, and the link runs at the highest speed that both sides support.

What does x4 or x16 mean?

It is the number of lanes in the link. Each lane carries data in both directions, so an x16 link has four times the bandwidth of an x4 link of the same generation.

What is PAM4 in PCIe 6.0?

PAM4 uses four voltage levels per symbol instead of two, carrying two bits at once. PCIe 6.0 uses it, together with forward error correction, to double the rate without doubling the signal frequency.

Check your understanding

What is closest to the effective one-direction bandwidth of a PCI Express 3.0 x16 link (8 GT/s per lane, 128b/130b encoding)?

  1. AAbout 128 GB/s
  2. BAbout 1 GB/s
  3. CAbout 16 GB/s
Show answer and explanation

Answer: C. About 16 GB/s

The effective rate of one lane is 8 Gb/s × 128/130 ≈ 7.88 Gb/s, or about 0.985 GB/s after dividing by 8. Sixteen lanes give about 15.8 GB/s, roughly 16 GB/s in one direction, or about 32 GB/s for both directions together. PCI Express bandwidth is the product of the generation's per-lane rate, the coding efficiency and the lane count. Packet headers and other overhead make the real figure somewhat lower.

For PCI Express generations 3 through 6, how does the per-lane signaling rate change with each generation?

  1. AIt roughly doubles each time (8 → 16 → 32 → 64 GT/s)
  2. BIt grows slowly by about 1.1× each time
  3. CThe rate stays the same; only the lane count grows
Show answer and explanation

Answer: A. It roughly doubles each time (8 → 16 → 32 → 64 GT/s)

PCI Express signaling rates have roughly doubled each generation: 8 GT/s for Gen 3, 16 GT/s for Gen 4, 32 GT/s for Gen 5 and 64 GT/s for Gen 6. With bandwidth doubling for the same lane count, the interface keeps up with faster GPUs, SSDs and networks. Generations are compatible, so a new device in an older slot runs at the speed both support.

Which is closest to the efficiency of the 128b/130b encoding adopted from PCI Express 3.0 onward?

  1. AAbout 80%
  2. BAbout 50%
  3. CAbout 98.5%
Show answer and explanation

Answer: C. About 98.5%

128b/130b encoding sends 128 data bits with a 2-bit header as 130 bits, so efficiency is 128/130 ≈ 98.5%, a big reduction in waste compared with 8b/10b's 80%. Transitions are ensured by scrambling the data (XOR with a fixed pseudo-random sequence) to mix 0s and 1s. This is why PCI Express 3.0 nearly doubled effective throughput while raising the signaling rate only from 5 to 8 GT/s.

  1. What is a characteristic of PAM4 (four-level pulse amplitude modulation), adopted in PCI Express 6.0?
  2. What happens when an x4 PCI Express SSD is plugged into a full-length x16 slot on a motherboard (assuming the slot is wired for at least x4)?
  3. What does it mean that a PCI Express lane is full duplex?

Practice I/O Interfaces & Buses questions

Key terms explained

PCI Express
A high-speed serial expansion interface connecting the CPU with GPUs, SSDs, network cards and more, also written PCIe. Lanes are bundled for bandwidth, and speed roughly doubles each generation.
NVMe
An interface standard for fast access to SSDs connected over PCI Express. It processes many commands in parallel and has lower latency than SATA, which was designed for HDDs.

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