I/O Interfaces & Buses

High-speed links such as 100-gigabit Ethernet are sometimes built by bundling, for example, four 25 Gb/s lanes. Which describes this approach?

  1. AThree of the four are spares; data actually travels on just one
  2. BThe same data is sent on all four and errors are fixed by majority vote
  3. CBecause per-lane speed is limited, data is spread across several SerDes lanes to reach the total bandwidth
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Answer: C. Because per-lane speed is limited, data is spread across several SerDes lanes to reach the total bandwidth

The speed of one SerDes lane is limited by circuit and channel technology. Spreading data across several lanes and realigning it in order at the receiver yields large total bandwidth. As per-lane speeds rise, the same bandwidth needs fewer lanes; for example, a single 100 Gb/s PAM4 lane can carry 100-gigabit traffic.

  • A. All lanes carry data.
  • B. The data is divided, not duplicated.
  • C. Correct. It is the same idea as PCI Express lanes.
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More I/O Interfaces & Buses questions

  1. What is the purpose of spread-spectrum clocking (SSC), used in PCI Express and elsewhere?
  2. What does it mean that a PCI Express lane is full duplex?
  3. Which describes the credit-based flow control used in PCI Express?
  4. In AI systems with many GPUs, why are dedicated high-speed GPU-to-GPU links (such as NVIDIA NVLink) used in addition to PCI Express?
  5. In PCI Express, sending many packets that each write 64 bytes yields effective bandwidth well below the theoretical figure. What is the main reason?