I/O Interfaces & Buses

Which describes a "lane" in PCI Express?

  1. AA unit of connection with one differential pair each for transmit and receive; lanes can be bundled for more bandwidth
  2. BA single wire that alternates between sending and receiving
  3. CThe physical length of the slot into which a PCI Express device is inserted
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Answer: A. A unit of connection with one differential pair each for transmit and receive; lanes can be bundled for more bandwidth

One PCI Express lane consists of a transmit differential pair and a receive differential pair, four wires in all, and carries data in both directions simultaneously. Bundling lanes as x4 or x16 spreads data across the lanes, so bandwidth grows in proportion to the lane count. Graphics cards commonly use x16, SSDs x4 and network cards x1 to x8.

  • A. Correct. Lanes are bundled as x1, x4, x16 and so on.
  • B. Transmit and receive use separate pairs at the same time (full duplex).
  • C. Slot length corresponds to lane count but is not the lane itself.
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More I/O Interfaces & Buses questions

  1. What is closest to the effective one-direction bandwidth of a PCI Express 3.0 x16 link (8 GT/s per lane, 128b/130b encoding)?
  2. For PCI Express generations 3 through 6, how does the per-lane signaling rate change with each generation?
  3. What is a characteristic of PAM4 (four-level pulse amplitude modulation), adopted in PCI Express 6.0?
  4. Why does forward error correction (FEC) become more important with PAM4 than with NRZ?
  5. What happens when an x4 PCI Express SSD is plugged into a full-length x16 slot on a motherboard (assuming the slot is wired for at least x4)?