Enter the per-pin transfer rate, the data bus width and the number of DIMMs, chips or stacks to get the peak memory bandwidth. Add an efficiency factor to see a rough estimate of the bandwidth you can actually use. Common standards are available as presets.
Results
Peak bandwidth
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Estimated effective bandwidth
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Per-pin data rate
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Bytes per nanosecond
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Typical standards compared (per unit)
Standard (unit)
MT/s
Bus width (bits)
Peak bandwidth
Peak values per DIMM for DDR4 and DDR5, per 64 bits for LPDDR5X, per chip for GDDR6 and per stack for HBM3. Transfer rates are typical speed grades for each standard; faster and slower parts also exist.
See it as a graph
Other inputs stay at their current values while the chosen input varies from 1/4 to 4 times its current value. The red dot is the current value.
How the bandwidth formula works
Peak memory bandwidth is the number of transfers each data pin makes per second (the transfer rate) times the number of pins (the bus width), divided by 8 to convert bits to bytes. DDR (double data rate) memory transfers data on both the rising and falling clock edges, so the transfer rate is twice the clock frequency. DDR4-3200 runs a 1,600 MHz clock for 3,200 MT/s. On a 64-bit bus that gives 3,200 × 64 ÷ 8 = 25,600 MB/s, or 25.6 GB/s. Confusing MHz with MT/s halves or doubles the answer.
Peak versus sustained bandwidth
Peak bandwidth is the theoretical ceiling with data flowing every cycle. A real DRAM loses time to refresh, which keeps the stored charge alive, to bank conflicts, where a new row must be opened in a busy bank, and to read/write turnaround when the bus changes direction. Sustained bandwidth is therefore lower than peak. It depends strongly on the access pattern, but roughly 60 to 90% of peak is a common rough guide: higher for streaming sequential reads, lower for random accesses and mixed reads and writes.
Wide and slow, or narrow and fast
Bandwidth comes either from more pins or faster pins. GDDR6 drives a narrow 32-bit bus per chip at 16 Gb/s per pin, giving 64 GB/s per chip. HBM3 instead connects a stack of DRAM dies through a very wide 1,024-bit bus; at a modest 6.4 Gb/s per pin a single stack reaches about 819 GB/s. HBM's short connections use less energy per bit, but it needs costly packaging such as a silicon interposer. GDDR mounts on an ordinary board, yet its fast signals make routing and power design harder.
The memory wall and the roofline
The memory wall is the gap that opens when processor compute performance grows faster than memory bandwidth and latency improve. Programs that do little arithmetic per byte moved leave the compute units idle waiting for data, so bandwidth sets their speed. The roofline model captures this: attainable performance is the lower of peak compute and bandwidth × arithmetic intensity (operations per byte). With 100 GB/s and one operation per byte, for example, performance cannot exceed 100 billion operations per second. Reusing data in caches to raise arithmetic intensity is the basic way to ease the bandwidth limit.
Peak bandwidth is transfer rate × bus width: 3,200 × 10⁶ transfers/s × 8 bytes = 25.6 GB/s. The name "DDR4-3200" gives the transfer rate (MT/s), while the module designation "PC4-25600" gives the bandwidth (MB/s). In practice, refresh, row switches and read/write turnarounds add idle time, so effective bandwidth is often about 70–80% of peak.
Processor performance at times grew more than 50% per year, but DRAM access latency has stayed at tens of nanoseconds, leaving CPUs waiting hundreds of cycles for data—the memory wall. Responses include multilevel caches, parallel memory access, prefetching, high-bandwidth memory such as HBM, and processing-in-memory, which computes near the data.
Bandwidth equals the amount of data in flight divided by latency (Little's law). With one miss, 64 B ÷ 100 ns = 0.64 GB/s; with 10 outstanding, 10 × 64 B ÷ 100 ns = 6.4 GB/s. Saturating memory bandwidth requires not just lower latency but memory-level parallelism, servicing many misses at once. 0.64 GB/s is the single-miss value unchanged, and 0.064 GB/s divides by 10 instead of multiplying.
FAQ
What is the bandwidth of DDR4-3200?
3,200 MT/s × 64 bits ÷ 8 = 25.6 GB/s. That is the peak for one 64-bit channel (one DIMM); two channels give 51.2 GB/s. Usable bandwidth is lower.
What is the difference between MT/s and MHz?
MHz is the clock frequency, while MT/s is millions of data transfers per second. DDR memory transfers on both clock edges, so MT/s is twice the clock frequency. DDR4-3200 uses a 1,600 MHz clock.
Why is a DDR5 DIMM split into two channels?
A DDR5 DIMM has two independent 32-bit subchannels (without ECC). The total width is the same 64 bits as DDR4, but the smaller, independent units allow more requests in flight, which tends to raise effective efficiency. One DDR5-6400 DIMM peaks at 51.2 GB/s.