I/O Interfaces & Buses

For PCI Express generations 3 through 6, how does the per-lane signaling rate change with each generation?

  1. AIt roughly doubles each time (8 → 16 → 32 → 64 GT/s)
  2. BIt grows slowly by about 1.1× each time
  3. CThe rate stays the same; only the lane count grows
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Answer: A. It roughly doubles each time (8 → 16 → 32 → 64 GT/s)

PCI Express signaling rates have roughly doubled each generation: 8 GT/s for Gen 3, 16 GT/s for Gen 4, 32 GT/s for Gen 5 and 64 GT/s for Gen 6. With bandwidth doubling for the same lane count, the interface keeps up with faster GPUs, SSDs and networks. Generations are compatible, so a new device in an older slot runs at the speed both support.

  • A. Correct. Bandwidth doubles each generation.
  • B. It grows much faster than that.
  • C. The per-lane rate rises.
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More I/O Interfaces & Buses questions

  1. What is a characteristic of PAM4 (four-level pulse amplitude modulation), adopted in PCI Express 6.0?
  2. Why does forward error correction (FEC) become more important with PAM4 than with NRZ?
  3. What happens when an x4 PCI Express SSD is plugged into a full-length x16 slot on a motherboard (assuming the slot is wired for at least x4)?
  4. Which statement about the structure of PCI Express is correct?
  5. How does communication in PCI Express work?