I/O Interfaces & Buses

Which statement about the structure of PCI Express is correct?

  1. AAll devices share one bus, and only one device can use it at a time
  2. BDevices connect to each other wirelessly
  3. CFrom the root complex on the CPU side, devices (endpoints) connect through switches in a tree of point-to-point links
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Answer: C. From the root complex on the CPU side, devices (endpoints) connect through switches in a tree of point-to-point links

Old PCI had several devices share one bus and compete for access. In PCI Express, the root complex, connected to the CPU and memory, is the root; switches branch out, and every link is a point-to-point connection between exactly two devices. Each link has its bandwidth to itself, so adding devices causes less contention, and signal quality is easier to maintain.

  • A. That is a shared-bus scheme like old PCI.
  • B. The connections are wired.
  • C. Correct. Each link is dedicated to two devices.
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More I/O Interfaces & Buses questions

  1. How does communication in PCI Express work?
  2. What does the PCI Express data link layer do about bit errors during transmission?
  3. How are the registers and memory of a PCI Express device made accessible to the CPU?
  4. What is a characteristic of MSI (message-signaled interrupts) used in PCI Express?
  5. What is the difference between bandwidth and latency in interface performance?