I/O Interfaces & Buses

Which correctly lists the three protocols that make up CXL?

  1. ACXL.usb, CXL.sata and CXL.hdmi
  2. BCXL.read, CXL.write and CXL.erase
  3. CCXL.io (PCI Express-equivalent I/O), CXL.cache (device caches CPU memory) and CXL.mem (CPU uses device memory)
Show answer and explanation

Answer: C. CXL.io (PCI Express-equivalent I/O), CXL.cache (device caches CPU memory) and CXL.mem (CPU uses device memory)

CXL.io is essentially PCI Express traffic used for device discovery, configuration, interrupts and so on. CXL.cache lets an accelerator cache CPU-side memory in its own cache while keeping coherence. CXL.mem lets the CPU read and write device memory like ordinary memory. A memory-expansion device uses CXL.io and CXL.mem, while an accelerator may use all three.

  • A. These are names of other external interfaces.
  • B. These sound like flash operations, not CXL protocols.
  • C. Correct. They are combined according to the use case.
Practice this topic Back to topic

More I/O Interfaces & Buses questions

  1. What is the role of equalizers (such as CTLE and DFE) in high-speed serial receivers?
  2. Which statement about the eye diagram used to assess high-speed serial signal quality is correct?
  3. Why does raising serial link speed make it harder to send signals over board traces of the same length, sometimes requiring retimers along the way?
  4. What does a requirement of "bit error rate (BER) at most 10^-12" for a high-speed serial link mean?
  5. Why are high-speed signal traces designed so that their characteristic impedance matches the transmit and receive circuits?