I/O Interfaces & Buses

What does the PCI Express data link layer do about bit errors during transmission?

  1. AIt does nothing and passes the data on until software notices
  2. BIt powers off the device when an error is found
  3. CIt adds a CRC to detect errors and, on error, signals that the packet was not received so it is resent
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Answer: C. It adds a CRC to detect errors and, on error, signals that the packet was not received so it is resent

The data link layer sends each packet with a sequence number and a CRC (cyclic redundancy check) code. The receiver checks the CRC and returns ACK if it is good or NAK if it is not; the sender keeps each packet until it is acknowledged and resends it on NAK. Thanks to this, even when the physical layer occasionally flips a bit, the upper layers and software receive correct data.

  • A. The data link layer detects and recovers errors.
  • B. It does not cut power.
  • C. Correct. It is retransmission based on ACK and NAK.
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More I/O Interfaces & Buses questions

  1. How are the registers and memory of a PCI Express device made accessible to the CPU?
  2. What is a characteristic of MSI (message-signaled interrupts) used in PCI Express?
  3. What is the difference between bandwidth and latency in interface performance?
  4. On a link with 10 GB/s bandwidth and 1 µs latency, roughly how long does it take to send 64 bytes once (time = latency + size ÷ bandwidth)?
  5. Which is most effective for speeding up a program that exchanges thousands of small pieces of data with a device one at a time?