I/O Interfaces & Buses

Which statement is correct about PCI Express link power saving (the L0s and L1 states of ASPM)?

  1. AThe link enters a low-power state while idle, but returning takes time and can add latency
  2. BIt raises link speed and increases power consumption
  3. CEven in the low-power state, data transfer speed is completely unaffected
Show answer and explanation

Answer: A. The link enters a low-power state while idle, but returning takes time and can add latency

A SerDes consumes power to keep the link alive even when no data is flowing. With ASPM, after a period of inactivity the link enters low-power states called L0s or L1, shutting down parts of the transmit and receive circuits. L1 saves more power but takes longer to exit. Laptops use it to extend battery life, while latency-sensitive servers sometimes turn it off.

  • A. Correct. It is configured by balancing power against responsiveness.
  • B. It is a power-saving feature.
  • C. The first transfer is delayed by the wake-up time.
Practice this topic Back to topic

More I/O Interfaces & Buses questions

  1. Why have high-speed connections between chips and boards moved from parallel transmission over many wires to serial transmission over a few fast wires?
  2. What is the role of a SerDes (serializer/deserializer) in high-speed serial links?
  3. Why do high-speed serial links use differential signaling, sending opposite signals on two wires?
  4. What is the role of the clock and data recovery (CDR) circuit in a high-speed serial receiver?
  5. What has been the purpose of 8b/10b encoding (sending 8 data bits as a 10-bit code) in serial links?