I/O Interfaces & Buses

What is the role of the clock and data recovery (CDR) circuit in a high-speed serial receiver?

  1. AIt amplifies a clock sent over a separate wire by the transmitter
  2. BIt extracts clock timing from the transitions of the received data and decides each bit at that timing
  3. CIt detects data errors and asks the transmitter to resend
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Answer: B. It extracts clock timing from the transitions of the received data and decides each bit at that timing

Sending the clock on a separate wire would introduce skew relative to the data. So in high-speed serial links, a CDR circuit watches where the data switches between 0 and 1, generates a clock of matching frequency and phase with a PLL or similar, and samples the data in the middle of each bit. This requires the data to contain transitions often enough, which line coding guarantees.

  • A. Most high-speed serial links do not send the clock on a separate wire.
  • B. Correct. No dedicated clock wire is needed.
  • C. Retransmission is a higher layer's job.
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More I/O Interfaces & Buses questions

  1. What has been the purpose of 8b/10b encoding (sending 8 data bits as a 10-bit code) in serial links?
  2. On a link using 8b/10b encoding with a signaling rate of 5 Gb/s, what is the effective data rate?
  3. Which is closest to the efficiency of the 128b/130b encoding adopted from PCI Express 3.0 onward?
  4. Which describes a "lane" in PCI Express?
  5. What is closest to the effective one-direction bandwidth of a PCI Express 3.0 x16 link (8 GT/s per lane, 128b/130b encoding)?