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NRZ vs PAM4: Key Differences Explained

NRZ is the most basic scheme, sending 1 bit per symbol with two signal levels. PAM4 sends 2 bits per symbol with four levels, so at the same bit rate the baud rate (symbols per second) is halved, avoiding the high-frequency loss of the channel. The trade-off is that three eyes are stacked vertically within the same amplitude, so each eye is about 1/3 as tall, a penalty of about 9.5 dB in SNR. For this reason, forward error correction (FEC) is almost essential in PAM4 links.

AspectNRZPAM4
Signal levelsTwo (0 and 1)Four (corresponding to 2-bit combinations such as 00, 01, 11, 10)
Bits per symbol1 bit2 bits
Baud rate at the same bit rateEqual to the bit rate (e.g. 64 GBd for 64 Gbit/s)Half the bit rate (e.g. 32 GBd for 64 Gbit/s)
Nyquist frequencyHalf the baud rate. Twice that of PAM4, so channel loss is largerHalf that of NRZ. Loss is smaller on the same channel
Eye openingOne large eyeThree eyes stacked vertically, each about 1/3 the height of NRZ
Required SNRBaselineAbout 9.5 dB (20 log₁₀ 3) worse at the same amplitude
FECOften none, or a lightweight code is enoughAlmost essential. A certain pre-FEC bit error rate is tolerated and corrected by FEC, at the cost of added latency
Transmit and receive circuitsRelatively simple. A single decision thresholdDecisions with three thresholds, and high linearity to keep the level spacing even. Many high-speed parts receive with an ADC and DSP
Bit mappingEach level corresponds to 1 bitAssigned with Gray coding so that an error to an adjacent level costs only 1 bit
Example standardsUp to PCI Express 5.0 (32 GT/s), Ethernet up to about 25 Gbit/s per lanePCI Express 6.0 (64 GT/s), Ethernet at 50 Gbit/s or 100 Gbit/s and above per lane, data-center optical transceivers

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

NRZ
When the speed per lane is up to tens of Gbit/s and there is margin in channel loss. When you want simple circuits and to avoid FEC latency.
PAM4
When 50 Gbit/s or more per lane is needed and NRZ's baud rate would be too high to tolerate the channel loss. Used together with FEC and strong equalization.
How to think about it
It is a choice between raising the baud rate and increasing the bits per symbol. PAM4 turns a frequency problem into an SNR problem and makes up the shortfall with FEC.

FAQ

Is PAM4 faster than NRZ?

At the same baud rate, PAM4 sends 2 bits per symbol, so its bit rate is doubled. Conversely, at the same bit rate, the baud rate can be halved. Either way, it is a scheme for using channel bandwidth efficiently, and it is correspondingly more vulnerable to noise.

Why is PAM4 about 9.5 dB worse in SNR?

Because the same voltage swing is divided into three intervals, the difference between adjacent levels is about 1/3 that of NRZ. This is equivalent to reducing the signal amplitude to 1/3, a penalty of 20 log₁₀ 3 ≈ 9.5 dB.

Why does PAM4 need FEC?

Because the level spacing is narrow and noise easily causes bit errors. Even if the pre-FEC bit error rate is fairly high, an error-correcting code corrects the errors in blocks so the link as a whole meets the required error rate. PCI Express 6.0 combines a lightweight, low-latency FEC with retransmission when errors are detected.

Why did PCI Express 6.0 switch to PAM4?

Sending 64 GT/s, twice the 32 GT/s of PCI Express 5.0, with NRZ would put the Nyquist frequency at 32 GHz, making board and connector losses too large. With PAM4, twice the transfer rate is obtained while staying at 32 GBd.

Check your understanding

What is a characteristic of PAM4 (four-level pulse amplitude modulation), adopted in PCI Express 6.0?

  1. AIt sends 1 bit per symbol using two voltage levels for 0 and 1
  2. BIt sends 2 bits per symbol with four voltage levels, doubling the bit rate at the same symbol rate
  3. CIt works only over optical fiber, not copper
Show answer and explanation

Answer: B. It sends 2 bits per symbol with four voltage levels, doubling the bit rate at the same symbol rate

Conventional NRZ uses two voltage levels to send 1 bit per symbol. PAM4 uses four levels to represent 00, 01, 10 and 11, sending 2 bits per symbol. Channels attenuate signals more at higher frequencies, so doubling the bit rate without raising the symbol rate is the advantage. PCI Express 6.0 reached 64 GT/s with PAM4 at the same symbol rate as Gen 5.

Why does forward error correction (FEC) become more important with PAM4 than with NRZ?

  1. APAM4 makes clock recovery impossible, so every bit is wrong
  2. BFitting four levels into the same swing shrinks the spacing to about one third, so noise causes more bit errors
  3. CPAM4 signals are encrypted and decryption errors must be fixed
Show answer and explanation

Answer: B. Fitting four levels into the same swing shrinks the spacing to about one third, so noise causes more bit errors

With the same voltage swing, two-level NRZ has the full swing between 0 and 1, but four-level PAM4 leaves only about one third of it between adjacent levels. The noise margin drops by roughly 9.5 dB, so bit errors become more likely. PCI Express 6.0 therefore adds a lightweight error-correcting code so the receiver can fix small errors before use.

Which statement about the eye diagram used to assess high-speed serial signal quality is correct?

  1. AIt overlays the waveforms of many bits; the wider and taller the central "eye" opening, the more margin there is
  2. BThe more closed the eye, the better the signal
  3. CIt is a chart for checking the health of human eyes
Show answer and explanation

Answer: A. It overlays the waveforms of many bits; the wider and taller the central "eye" opening, the more margin there is

An eye diagram slices the waveform at each bit period and overlays the pieces. An eye-shaped gap appears between the 0 and 1 traces; its height represents the margin against noise and its width the margin against timing variation (jitter). Channel loss, reflections and jitter close the eye. The receiver decides bits at the center of the eye, so its opening is a measure of quality.

  1. With PAM4, which is closest to the symbol rate (symbols per second) when sending a signal of about 106 Gb/s per wavelength (including error-correction coding, etc.)?
  2. When PAM4 is used with the intensity modulation/direct detection (IM-DD) scheme widely used for optical links within data centers, what is varied among four values?
  3. High-speed links such as 100-gigabit Ethernet are sometimes built by bundling, for example, four 25 Gb/s lanes. Which describes this approach?

Practice I/O Interfaces & Buses questions

Key terms explained

NRZ
Non-return-to-zero: the most basic signaling scheme, sending 1 bit per symbol with two voltage levels.
PAM4
Four-level pulse amplitude modulation, sending 2 bits per symbol. It doubles the bit rate at the same symbol rate but reduces noise margin.
Eye diagram
A plot overlaying many bit periods of a waveform. The height of the central eye shows noise margin and its width shows timing margin.
SerDes
Serializer/deserializer: a circuit that turns parallel on-chip data into a fast serial bit stream for transmission and restores the parallel data at the receiver. It is the heart of high-speed serial physical layers.

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