I/O Interfaces & Buses
How are the registers and memory of a PCI Express device made accessible to the CPU?
- AAt boot the OS or firmware reads the size each device requests and assigns an address in its BAR (base address register), making it visible as memory addresses
- BEach device has a fixed address set at manufacture
- CThe CPU cannot read device registers; everything goes through DMA
Show answer and explanation
Answer: A. At boot the OS or firmware reads the size each device requests and assigns an address in its BAR (base address register), making it visible as memory addresses
A PCI Express device reports the sizes of its registers and memory through its BARs. At boot, the firmware or OS examines every connected device (enumeration) and assigns addresses so they do not collide. Afterward the CPU operates the device by reading and writing those addresses like ordinary memory. A device plugged in later is assigned addresses the same way.
- A. Correct. They are used as memory-mapped I/O.
- B. Fixed addresses would collide between devices.
- C. The CPU reads and writes registers directly.