SRAM and flash memory

In SRAM, which correctly describes the "data retention voltage" that sets the lower limit when the supply is lowered during standby to reduce leakage?

  1. AThe lowest supply voltage at which the cell keeps its contents without being read or written
  2. BThe maximum voltage needed for reading
  3. CThe voltage needed for writing
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Answer: A. The lowest supply voltage at which the cell keeps its contents without being read or written

In standby, when it is neither read nor written, an SRAM cell can retain data at voltages below its normal operating voltage. The lowest voltage at which it does not lose data is the data retention voltage (DRV), and lowering the supply close to it in standby greatly reduces leakage.

  • A. Correct. It is the lowest supply voltage that preserves the contents.
  • B. The data retention voltage concerns the lowest voltage.
  • C. Writing requires a higher voltage than retention.
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More SRAM and flash memory questions

  1. In a 6T SRAM cell, which design is needed so that the cell contents are not flipped during a read (to prevent read upset)?
  2. Which is an example of a "write assist" technique to prevent SRAM write failures at low voltage?
  3. In multi-level (MLC or TLC) NAND flash, why are the bit patterns assigned to adjacent threshold-voltage states chosen to differ by only one bit?
  4. In 3D NAND, what is the structure called in which the edge of the stack is shaped into steps so that each layer's word line can be connected?
  5. In 3D NAND, what is the main advantage of placing peripheral circuits such as sense amplifiers beneath the memory array (CMOS under Array and similar)?