SRAM and flash memory

In multi-level (MLC or TLC) NAND flash, why are the bit patterns assigned to adjacent threshold-voltage states chosen to differ by only one bit?

  1. ATo make erasing unnecessary
  2. BSo that misreading a state as its neighbor causes only a single-bit error
  3. CTo double the write speed
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Answer: B. So that misreading a state as its neighbor causes only a single-bit error

In multi-level cells, the threshold voltage distributions can overlap with neighboring states, causing misreads. Assigning bit patterns with a Gray code, in which adjacent states differ by only one bit, means a misread produces only a single-bit error that ECC can easily correct.

  • A. Erasing is still necessary regardless of the assignment.
  • B. Correct. A Gray code limits the error to a single bit.
  • C. The bit assignment does not double the write speed.
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More SRAM and flash memory questions

  1. In 3D NAND, what is the structure called in which the edge of the stack is shaped into steps so that each layer's word line can be connected?
  2. In 3D NAND, what is the main advantage of placing peripheral circuits such as sense amplifiers beneath the memory array (CMOS under Array and similar)?
  3. Which correctly describes the structure of a typical six-transistor SRAM cell?
  4. Compared with NOR flash, which is a characteristic of NAND flash memory?
  5. In flash memory, what is the scheme that stores 3 bits of information in one memory cell called?