SRAM and flash memory

In recent advanced processes, what is the most appropriate reason SRAM cell area has become harder to shrink than logic?

  1. ASRAM is sensitive to variations in transistor characteristics, making it hard to secure margins for stable reading and writing
  2. BSRAM does not use transistors
  3. CSRAM needs a large capacitor
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Answer: A. SRAM is sensitive to variations in transistor characteristics, making it hard to secure margins for stable reading and writing

An SRAM cell combines six near-minimum-size transistors and relies on the balance of their characteristics for stability. With scaling, transistor variation becomes relatively larger, making it hard to secure read and write margins, so SRAM cell area cannot shrink as much as logic.

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More SRAM and flash memory questions

  1. Which technique do NAND flash controllers use to cope with the increase in read errors that comes with storing more bits per cell?
  2. What is a typical use of NOR flash memory?
  3. Which correctly describes garbage collection in an SSD?
  4. In an SRAM read, what is the operation called that charges the bit lines in advance to the supply voltage or similar?
  5. Which electron injection mechanism is mainly used for writing (programming) NAND flash memory?