SRAM and flash memory

In NAND flash, what is the phenomenon in which repeatedly reading the same block gradually shifts the threshold voltages of cells that are not being read?

  1. AWear leveling
  2. BRead disturb
  3. CGarbage collection
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Answer: B. Read disturb

During a NAND read, a voltage is applied to unselected cells to make them conduct, so repeated reads cause weak programming and their threshold voltages rise. This is called read disturb. The controller tracks the number of reads and rewrites data when necessary.

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More SRAM and flash memory questions

  1. In QLC (4 bits per cell) NAND flash, how many threshold voltage states must one cell distinguish?
  2. In TLC and QLC SSDs, what is the main purpose of using part of the space as SLC to absorb writes temporarily?
  3. What problem tends to occur as the supply voltage of SRAM is lowered?
  4. What is the advantage of an 8T SRAM cell, which adds read-only transistors to a 6T SRAM cell?
  5. In flash memory erase, what happens to a cell's threshold voltage when electrons are removed from the floating gate or similar layer?