SRAM and flash memory

Which is an example of a "write assist" technique to prevent SRAM write failures at low voltage?

  1. APulling the bit line on the 0 side slightly below ground during a write
  2. BRaising the cell supply voltage during a write
  3. CLowering the word-line voltage
Show answer and explanation

Answer: A. Pulling the bit line on the 0 side slightly below ground during a write

At low voltage, the access transistor's drive becomes insufficient to overpower the cell's pull-up, so writes tend to fail. Pulling the bit line on the side being written to 0 down to a negative voltage (negative bit line) increases the access transistor's drive and makes writing easier. Lowering the cell supply during writes is also used.

  • A. Correct. A negative bit line assists the write.
  • B. Lowering, not raising, the cell supply during a write makes the cell easier to flip.
  • C. Lowering the word line weakens the access transistor and makes writing harder.
Practice this topic Back to topic

More SRAM and flash memory questions

  1. In multi-level (MLC or TLC) NAND flash, why are the bit patterns assigned to adjacent threshold-voltage states chosen to differ by only one bit?
  2. In 3D NAND, what is the structure called in which the edge of the stack is shaped into steps so that each layer's word line can be connected?
  3. In 3D NAND, what is the main advantage of placing peripheral circuits such as sense amplifiers beneath the memory array (CMOS under Array and similar)?
  4. Which correctly describes the structure of a typical six-transistor SRAM cell?
  5. Compared with NOR flash, which is a characteristic of NAND flash memory?