SRAM and flash memory

In QLC (4 bits per cell) NAND flash, how many threshold voltage states must one cell distinguish?

  1. A4
  2. B8
  3. C16
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Answer: C. 16

Storing N bits per cell requires distinguishing 2ᴺ threshold voltage states. For QLC that is 2⁴ = 16 states; SLC has 2, MLC 4 and TLC 8. The more states, the narrower the spacing between them, and the more precise reading and writing must be.

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More SRAM and flash memory questions

  1. In TLC and QLC SSDs, what is the main purpose of using part of the space as SLC to absorb writes temporarily?
  2. What problem tends to occur as the supply voltage of SRAM is lowered?
  3. What is the advantage of an 8T SRAM cell, which adds read-only transistors to a 6T SRAM cell?
  4. In flash memory erase, what happens to a cell's threshold voltage when electrons are removed from the floating gate or similar layer?
  5. Which is closest to the number of layers in recent 3D NAND?