SRAM and flash memory

In flash memory erase, what happens to a cell's threshold voltage when electrons are removed from the floating gate or similar layer?

  1. AIt rises
  2. BIt falls
  3. CIt does not change
Show answer and explanation

Answer: B. It falls

When the floating gate holds electrons (negative charge), a larger gate voltage is needed to form a channel, so the threshold voltage is high. Removing electrons during erase lowers the threshold voltage, and injecting electrons during programming raises it.

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More SRAM and flash memory questions

  1. Which is closest to the number of layers in recent 3D NAND?
  2. In NAND flash, what is the role of the select transistors placed at both ends of the series-connected memory cells?
  3. When writing to an SRAM cell, one bit line is pulled down to 0 V to flip the cell's state. What condition is required of the access transistor?
  4. In NAND flash, which programming method applies repeated program pulses with gradually increasing voltage, checking the threshold voltage after each one?
  5. Which command notifies an SSD of space freed by files deleted by the OS, making garbage collection more efficient?