SRAM and flash memory
Which technique do NAND flash controllers use to cope with the increase in read errors that comes with storing more bits per cell?
- AData encryption
- BPowerful error-correcting codes (such as LDPC codes)
- CFaster clocks
Show answer and explanation
Answer: B. Powerful error-correcting codes (such as LDPC codes)
The more bits stored per cell, the narrower the gaps between threshold voltage distributions, and the more read errors occur. NAND flash controllers therefore use error-correcting codes with strong correction capability, such as LDPC codes, to ensure data reliability.