SRAM and flash memory

What problem tends to occur as the supply voltage of SRAM is lowered?

  1. AThe margin for stable reading and writing (noise margin) shrinks, making malfunctions more likely
  2. BAccess becomes too fast
  3. CStorage capacity increases
Show answer and explanation

Answer: A. The margin for stable reading and writing (noise margin) shrinks, making malfunctions more likely

An SRAM cell operates on the stability of its inverter latch and the balance of drive strength with the access transistors. Lowering the supply voltage reduces the noise margin, and with transistor variation, data is more likely to flip during reads or writes are more likely to fail.

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More SRAM and flash memory questions

  1. What is the advantage of an 8T SRAM cell, which adds read-only transistors to a 6T SRAM cell?
  2. In flash memory erase, what happens to a cell's threshold voltage when electrons are removed from the floating gate or similar layer?
  3. Which is closest to the number of layers in recent 3D NAND?
  4. In NAND flash, what is the role of the select transistors placed at both ends of the series-connected memory cells?
  5. When writing to an SRAM cell, one bit line is pulled down to 0 V to flip the cell's state. What condition is required of the access transistor?