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Setup Time vs Hold Time: Key Differences Explained

Both are timing conditions for a flip-flop to capture data correctly, but they guard in opposite directions. Setup time is how long data must be stable before the clock edge, and checks that data is not too slow. Hold time is how long data must stay unchanged after the edge, and checks that data is not too fast. The setup condition includes the clock period, so slowing the clock fixes it, but hold compares the same edge, so lowering the frequency does not fix it.

AspectSetup timeHold time
DefinitionThe minimum time data must be stable before the active clock edgeThe minimum time data must stay unchanged after the active clock edge
What it checksWhether data is too slow: does it arrive in time for the next edgeWhether data is too fast: does new data slip in at the same edge
Edges comparedThe launch edge and the capture edge one period laterThe same edge at launch and capture
Delay used for the checkMaximum (max) delay: the slowest pathMinimum (min) delay: the fastest path
Condition (rough)tcq(max) + tlogic(max) + tsu ≤ T + tskewtcq(min) + tlogic(min) ≥ th + tskew (tskew is positive when the capture clock is late)
Relation to clock frequencyThe period T appears in the equation. It sets the maximum operating frequencyThe period does not appear in the equation. Independent of frequency
Effect of clock skewA late capture clock increases the marginA late capture clock reduces the margin
How to fix violationsReduce logic levels, switch to stronger or faster low-threshold cells, place cells closer, split the path with pipelining, slow the clockInsert delay buffers in the data path, switch to slower high-threshold cells, adjust clock skew
Corners where violations are likelySlow conditions: slow process, low voltage, high temperature (in advanced processes, low temperature may be slower)Fast conditions: fast process, high voltage, low temperature, etc.
If found after the chip is madeThe chip works if the clock is slowed, at lower performanceLowering the frequency does not fix it, and the chip does not work correctly. A fix often requires a design change

Figures are typical orders of magnitude and vary by process generation and product.

When to use which

Setup time
When determining the maximum operating frequency, or finding and speeding up slow paths. In static timing analysis, it is checked with max delay and slow corners.
Hold time
When paths between flip-flops are short or clock skew is large. It is checked with min delay and fast corners, and is usually fixed after building the clock tree.
Both together
Fixing one can make the other worse. Inserting too many buffers to fix hold reduces setup margin, so both must be met at the same time in all corners.

FAQ

Why can't a hold violation be fixed by slowing the clock?

The hold condition compares the same clock edge at launch and capture, so the clock period does not appear in the equation. It is fixed by changing the path delay itself, for example by inserting buffers in the data path to delay it.

Why is max delay used for setup checks and min delay for hold checks?

For setup, the question is whether data arriving at its slowest still makes it before the next edge, so maximum delay is checked. For hold, the question is whether new data arriving at its fastest corrupts the previous data, so minimum delay is checked.

What happens if setup or hold time is not met?

The flip-flop captures a wrong value, or its output enters a metastable state, staying neither 0 nor 1 for a while. This cannot be completely avoided for asynchronous signals, so they are received through a synchronizer of two or more flip-flops.

Check your understanding

Which correctly describes the setup time of a flip-flop?

  1. AThe minimum time data must be held after the clock edge
  2. BThe minimum time the data input must be stable before the clock edge
  3. CThe time from power-on until it starts operating
Show answer and explanation

Answer: B. The minimum time the data input must be stable before the clock edge

For a flip-flop to capture correctly, data must be stable for a certain time before the clock edge—the setup time. A violation occurs if the data-path delay exceeds the clock period minus the setup time, and it can be fixed by slowing the clock. The time data must remain stable after the edge is the hold time. Violating either can capture wrong values or cause metastability.

Which correctly describes the hold time of a flip-flop?

  1. AThe time the data input must be stable before the active clock edge
  2. BThe time from the clock edge until the output changes
  3. CThe time the data input must remain unchanged after the active clock edge
Show answer and explanation

Answer: C. The time the data input must remain unchanged after the active clock edge

Hold time is the minimum time data must stay stable after the clock edge. If the path from one flip-flop to the next is too short, new data launched by the same edge arrives too early and violates hold. Because it does not depend on the clock period, slowing the clock cannot fix it; the remedy is inserting buffers to add delay. A hold violation found after manufacturing can render the chip unusable, so design-time verification is critical.

Which correctly describes clock skew in a synchronous circuit?

  1. AVariation of the clock frequency over time
  2. BThe difference in the time the clock signal arrives at different flip-flops
  3. CThe clock signal voltage exceeding the supply voltage
Show answer and explanation

Answer: B. The difference in the time the clock signal arrives at different flip-flops

Clock skew is the difference in arrival times of the same clock at different flip-flops, caused by differences in wire length and load. A late capture clock helps setup but hurts hold, and vice versa. Clock tree synthesis (CTS) builds the chip-wide clock tree, balancing buffer placement and wire lengths to keep skew within tens of picoseconds. Variation of the period over time is jitter.

  1. In static timing analysis, which timing violation occurs when a signal changes too soon after the clock edge, so a flip-flop cannot correctly hold the previous data?
  2. Why is static timing analysis performed under multiple conditions combining process variation, supply voltage and temperature?
  3. When checking whether the receiver's hold time is met, which value of the transmitter's clock-to-output delay should be used?

Practice Logic circuits questions

Key terms explained

Setup time
The minimum time before the active clock edge during which a flip-flop's data input must be stable. Paths that cannot meet it limit the maximum operating frequency.
Hold time
The minimum time after the active clock edge during which a flip-flop's data input must stay unchanged. Violations are not fixed by lowering the clock frequency, so delay is added to the path.
Clock skew
The difference in arrival time of the same clock signal at different flip-flops. Because it changes setup and hold margins, clock tree synthesis keeps it small.
STA (static timing analysis)
A method that calculates the delay of every path in a circuit without test patterns and checks that timing constraints are met.
Metastability
A state in which a flip-flop's output stays between 0 and 1 for a while when setup or hold time is violated. Asynchronous signals are passed through two flip-flops (a synchronizer) to guard against it.

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