Interconnect processes

What problems occur when copper filling is incomplete and a void remains in a via?

  1. AHigher resistance or open circuits, and reduced electromigration resistance
  2. BThe wiring emits light
  3. CThe capacitance between wires becomes zero
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Answer: A. Higher resistance or open circuits, and reduced electromigration resistance

A void in a via narrows the current path, raising resistance and in severe cases causing an open circuit. Current density also becomes locally high, making electromigration failures more likely. Void-free filling is achieved by optimizing plating-bath additives and conditions.

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More Interconnect processes questions

  1. If the spacing between adjacent wires in the same layer is halved, approximately how does the capacitance between them change? (Approximate as parallel plates.)
  2. Which technique forms vias self-aligned to wiring trenches to tolerate misalignment between upper and lower wiring layers?
  3. For wiring with a resistivity of 2 µΩ·cm, 1 mm long, with width and thickness of 100 nm each, approximately what is the resistance?
  4. Where are voids due to electromigration likely to form?
  5. In highly scaled LSIs, how has wiring delay trended compared with gate delay?