Calculate the impedance a power delivery network (PDN) must meet from the supply voltage, the allowed voltage ripple and the step in load current. Enter a decoupling capacitor's capacitance, ESR, ESL and count to see its impedance versus frequency and the range where it meets the target.
Results
Target impedance Zt
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Self-resonant frequency 1/(2π√(LC))
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|Z| at self-resonance = ESR/N
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Lower edge of |Z| < Zt
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Upper edge of |Z| < Zt
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Minimum count for ESR/N ≤ Zt
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With this many capacitors, the impedance never falls below the target impedance.
Both axes are logarithmic. The blue line is the impedance of N capacitors in parallel, the dashed line is the target impedance and the red dot marks the self-resonant frequency.
Each capacitor is modeled as C, ESR and ESL in series, and N identical capacitors in parallel give (ESR + jωESL + 1/(jωC))/N. The voltage regulator (VRM), board and package inductance, plane capacitance and on-die capacitance are not included. ESR and ESL depend on mounting and frequency, and ceramic capacitors lose capacitance with DC bias and temperature, so check the manufacturer's data.
See it as a graph
Other inputs stay at their current values while the chosen input varies from 1/4 to 4 times its current value. The red dot is the current value.
The idea of target impedance
When the load current steps by ΔI, a supply path with impedance Z lets the voltage move by about Z·ΔI. Keeping that within the allowed ripple requires an impedance at or below Zt = V × ripple / ΔI. With the defaults of 1.0 V, 5% and 10 A, Zt = 1.0 × 0.05 / 10 = 5 mΩ. At 0.75 V and 3% with the same 10 A, Zt is 2.25 mΩ. At constant power, a lower voltage means more current, so the target impedance falls with the square of the voltage, making low-voltage, high-current chips hard to supply.
Self-resonance, ESR and ESL
A real capacitor has an equivalent series resistance (ESR) and an equivalent series inductance (ESL) besides its capacitance. Its impedance is set by 1/(2πfC) at low frequencies and by 2πf·ESL at high frequencies; at the self-resonant frequency 1/(2π√(LC)) the two cancel and only the ESR remains. With the default 1 µF and 0.5 nH, self-resonance is at about 7.12 MHz, where ten in parallel give 10 mΩ / 10 = 1 mΩ. They stay below the 5 mΩ target from about 2.76 MHz to 18.4 MHz.
How count and ESL set the range
Putting N identical capacitors in parallel divides the impedance by N at every frequency. The smallest count with ESR/N ≤ Zt is 2 with the defaults, but two capacitors only touch 5 mΩ at the single self-resonant point. The upper edge is set mainly by ESL/N: raising the capacitance to 10 µF leaves it almost unchanged at about 15.9 MHz and only lowers the lower edge to about 318 kHz. Halving ESL to 0.25 nH extends the upper edge to about 34.2 MHz. At high frequencies, lowering inductance matters more than adding capacitance.
Real PDNs and anti-resonance
A real PDN divides the frequency range among parts: the voltage regulator (VRM) and bulk capacitors at low frequencies, then board ceramic capacitors, package capacitors and on-die capacitance. This tool models a single capacitor type. When capacitors of different values are paralleled, the ESL of the larger one and the capacitance of the smaller one can form a parallel resonance, an anti-resonance where the impedance peaks sharply. This is a key pitfall of PDN design, so designs are checked with analysis that includes plane capacitance and interconnect.
BTo suppress supply voltage fluctuation (noise) by supplying charge when current changes suddenly
CTo make the chip emit light
Show answer and explanation
Answer: B. To suppress supply voltage fluctuation (noise) by supplying charge when current changes suddenly
An IC's supply current changes abruptly with activity, and the inductance L of the power path produces L·di/dt voltage swings. Decoupling capacitors placed near the chip supply charge during sudden current changes, suppressing supply fluctuations. Because each location is effective in a different frequency range, capacitors of different sizes are distributed on the die, in the package and on the board. Amplifying signals is not their role.
ATo lower the DC resistance of the supply line and thereby reduce the IC's average current consumption
BBecause longer wiring reduces the capacitance of the capacitor itself accordingly
CTo reduce wiring inductance and suppress supply voltage fluctuations caused by rapid current changes
Show answer and explanation
Answer: C. To reduce wiring inductance and suppress supply voltage fluctuations caused by rapid current changes
Digital circuits draw large currents from the supply for short periods on every clock. The wiring from the supply to the IC has inductance L, which produces a voltage drop of L × di/dt in response to current changes. For example, with 2 nH of wiring and a current change of 0.1 A/ns, the supply voltage drops by as much as 0.2 V. Placing the capacitor right next to the pin lets it supply this current over a short path. Wiring length does not change the capacitance value itself; the problem is the inductance of the path.
A capacitor's impedance is 1/(2πfC), shrinking as frequency rises: it blocks DC and passes high frequencies more easily. For example, 0.1 µF is about 1.6 kΩ at 1 kHz and about 0.16 Ω at 10 MHz. This makes capacitors ideal as bypass capacitors placed near IC supply pins to shunt high-frequency noise to ground, and in filters. Real capacitors have parasitic inductance, though, so their impedance rises again at very high frequencies.
An LC circuit resonates where the inductor's reactance 2πfL equals the capacitor's 1/(2πfC), giving f = 1/(2π√(LC)); for L = 10 µH and C = 100 pF, about 5 MHz. Series resonance gives minimum impedance and parallel resonance maximum. LC resonance is used in radio tuning, LC oscillators, filters, and antenna circuits for wireless power and RFID.
FAQ
Must the target impedance be met at all frequencies?
The aim is to meet it over the frequencies contained in the load's current changes. The regulator's (VRM) control loop covers low frequencies, and above that bulk capacitors, ceramic capacitors and package and on-die capacitance take over in turn. At high frequencies, package inductance makes board capacitors ineffective, so on-die capacitance has to carry the load.
Is a lower ESR always better?
A lower ESR reduces the impedance at self-resonance, but a very low ESR makes anti-resonance peaks between different capacitors, and resonances with the power planes, sharper and higher. Designs therefore sometimes rely on moderate ESR to damp resonances, or use capacitors with deliberately higher ESR.
Is one large capacitor or several smaller ones better?
At high frequencies ESL dominates, so several capacitors in parallel, which divide the ESL by N, are often better. Each capacitor also adds its own trace and via inductance, though, so layout details such as placing power and ground vias close together matter. Change N and ESL in this tool to see how the upper edge of the range moves.