How DRAM Works: Cells, Refresh and Sense Amplifiers

Where you see it: the "16 GB of memory" in your PC

A laptop's spec sheet may say "16 GB DDR5 memory." A phone's may say "8 GB RAM." This "memory" or "RAM" is made of DRAM chips. It is where programs and data sit while the CPU works on them.

In a desktop PC, several DRAM chips are mounted on a long, thin circuit board. The board plugs into a slot. The most common form of this board is called a DIMM. You can add capacity later by plugging in more boards.

In phones and thin laptops, the DRAM chips are soldered straight onto the main board. This saves space, but you cannot add more later. Data center servers carry far more DRAM than PCs do. The chips that run AI calculations (GPUs) also have parts made of stacked DRAM placed right beside them.

The shapes and places differ, but the way they store data is the same. This article walks through it step by step.

How it works 1: one bit is a "switch" plus a "container"

DRAM stores one 0-or-1 value (one bit) with just two parts. The first is a switch that connects or cuts off a path for electricity. This switch is a transistor ("What Is a Transistor?").

The second is a tiny container that holds charge, a part called a capacitor ("What Is a Capacitor?"). A full container means 1, and an empty one means 0. While the switch is off, the container is cut off from the outside and keeps its charge inside.

This pair, which stores one bit, is called a "cell." With only two parts, a cell can be made very small. A single chip holds billions of these cells.

A signal line turns the switches on. It connects to a whole horizontal row of cells at once. This line is called the word line. Sending a signal on one word line turns on every switch in that row at the same time.

The other side of each switch connects to a second line that runs vertically. Data goes in and out of the cell through this line. It is called the bit line.

Robert Dennard of IBM came up with this design in 1966. Today's DRAM still uses the same basic form. In 1970, Intel released a product called the "1103." The 1103 used a slightly different cell, with three transistors per bit. Even so, it became the first chip memory that could compete on price with the main memory of the day. That memory stored bits in tiny rings of magnetic material (magnetic core memory).

How it works 2: the charge leaks, so it keeps being rewritten

The charge in the container slowly leaks away, even with the switch off. Neither the switch nor the container can stop electricity completely. Left alone, a cell that stored a 1 would become impossible to tell apart from a 0.

So DRAM reads each cell before its contents fade, and writes the same value back. This is called refresh. The "D" in DRAM stands for "dynamic." It means the memory needs constant upkeep.

The refresh interval is set by JEDEC, an industry group that writes chip standards. In the DDR4 generation, every cell is rewritten once within 64 milliseconds (0.064 seconds), up to 85°C. Heat makes the charge leak faster, so above 85°C the interval drops to 32 milliseconds. In the newer DDR5, it is 32 milliseconds even up to 85°C.

If every cell were rewritten at once, the memory could not be used during that time. So in DDR4, a circuit on the CPU side sends 8,192 refresh commands every 64 milliseconds. Each command makes the chip rewrite only some of its cells. That works out to one command about every 7.8 microseconds (a microsecond is a millionth of a second). Refreshes are slipped in between normal reads and writes.

When the power goes off, refresh stops too. The leaked charge does not come back, so the contents fade away. This is why DRAM loses its data when the power is off.

How it works 3: reading drains the cell, so a sense amplifier writes it back

The container in a cell is tiny and holds very little charge. The bit line, on the other hand, is a long line connected to many cells. When the switch turns on, the container's charge spreads out over the bit line and gets diluted. The line's voltage moves only very slightly.

So before reading, the bit line is set to a voltage exactly halfway between 0 and 1. This preparation step is called precharge. If the cell holds a 1, the voltage rises a little. If it holds a 0, the voltage falls a little.

A circuit detects this small rise or fall and widens it into a clear 0 or 1 voltage. It is called a sense amplifier. The name means it "senses" a small signal and "amplifies" it.

The charge that spread over the bit line does not flow back into the container by itself. In other words, reading DRAM destroys the stored value. But the clear value from the sense amplifier goes straight back through the bit line into the container. Reading doubles as rewriting. Refresh uses this same mechanism.

To keep things simple, this article skips the circuit inside the sense amplifier. What matters is its job: "detect a tiny difference, widen it, and write it back along the way."

How it works 4: rows and columns, and what "random access" means

The cells in a chip are laid out in a grid, like squares on graph paper. The horizontal lines of cells are rows, and the vertical lines are columns. You pick a location by number: "row such-and-such, column such-and-such."

To read, the chip first picks one row with its word line. This is called "opening a row." Every cell in that row is then read out, through its own bit line, into the sense amplifiers. Next, the column number selects just the part that is needed and sends it out. In Micron's DDR4 chip, for example, one row holds 8,192 bits (1 KB).

Inside a row that is already open, you can keep reading fast just by changing the column. Moving to a different row takes longer. The chip must close the current row, precharge the bit lines again, and then open the new row.

RAM stands for "random-access memory." Here, "random" does not mean haphazard. It means you can read or write any numbered location directly, without stepping through the others in order. The name contrasts it with media like magnetic tape, which must be wound forward from the start to reach a spot.

But as shown above, reading is fast within the same row and slower across rows. "Random access" does not mean "exactly the same speed everywhere."

A single chip contains several of these grids. Each grid that can work on its own is called a bank. While one bank has a row open, another bank can get ready for the next access. This hides some of the waiting time.

DRAM vs SRAM vs flash memory

Besides DRAM, there are other major types of chip memory. Inside the CPU is a cache, which keeps copies of often-used data, and it uses SRAM ("How Does CPU Cache Work?"). Phone storage and SSDs use flash memory.

SRAM usually stores one bit in a circuit of six transistors. It keeps its value as long as the power is on, so it needs no refresh. It is fast, but each bit takes up more space, so it does not suit large capacities.

Flash memory stores data by trapping electrons in a tiny room surrounded by a film that does not conduct electricity. Its data survives power-off. But reading and writing are much slower than DRAM, and it can be rewritten only a limited number of times ("How Do SSDs Work?").

The wait times are rough figures as seen from the CPU (1 ns, or nanosecond, is a billionth of a second). The SRAM figure is for a cache inside the CPU. The flash figure is for a typical chip used in SSDs and similar devices. Real values vary by product. The three types are good at different things, so computers use them together. For detailed tables, see "DRAM vs SRAM" and "DRAM vs NAND Flash."

DDR and LPDDR: how to read generation names

DRAM for PCs and servers comes in generations. Each generation is a set of rules for how the DRAM exchanges data with the CPU. Today's standard approach is DDR SDRAM. The "DDR5" on a spec sheet means its fifth generation.

DRAM and the CPU send data in step with a signal that ticks at a steady rhythm. This signal is called the "clock." DDR stands for "double data rate." It sends data on both the rising and the falling edge of each clock wave, so it sends twice per clock tick.

The table below shows when JEDEC published the standard for each generation, and the speed of one data line. MT/s means "million transfers per second." So 3,200 MT/s is 3.2 billion transfers per second.

The speeds are the ranges each standard first set (for DDR5, a later update is included). Before DDR3, there were also the DDR and DDR2 generations. Each new generation changes both the slot shape and the electrical rules. So a DDR5 module will not fit in a DDR4 slot.

Phones and thin laptops use LPDDR, a version redesigned to use less power. LP stands for "low power." It lowers the voltage and lets unused parts rest in small pieces. In July 2025, JEDEC announced a new generation, LPDDR6.

GDDR for graphics and HBM, which stacks chips, are also DRAM inside. What differs is how the chips are arranged and how they connect to the CPU or GPU. "What Is HBM?" covers HBM in detail.

Who makes DRAM?

Only a handful of companies in the world can make DRAM in large volumes. According to the research firm TrendForce, Samsung of South Korea led revenue share in April to June 2026, with 39.4%. SK hynix of South Korea was second with 24.9%, and Micron of the US was third with 23.3%. Together, the three hold about 90%.

The ranking shifts with price swings and with sales of HBM for AI. In the same firm's figures, SK hynix passed Samsung for first place in January to March 2025. When you see market shares in the news, check when the figures are from and who compiled them.

Japan once had its own DRAM maker, Elpida Memory. Micron bought it in 2013. With that deal, a DRAM factory in Hiroshima, Japan, also became Micron's.

Common misconceptions

By the numbers

This chip moves 8 bits in or out for each column number. Multiplying the numbers for the 8 Gb (gigabit) chip gives 8,589,934,592 bits. That is 2 multiplied by itself 33 times, and memory "8 Gb" is counted this way. Eight bits make one byte, so eight of these chips side by side make 8 GB of memory.

A DDR5 module's path has 64 lines in total (8 bytes' worth). DDR5-6400 is a product where each line sends 6.4 billion times per second (6,400 MT/s). Eight bytes times 6.4 billion gives 51.2 GB per second. This is the theoretical maximum, and the amount you can actually use is somewhat lower.

Learn more

• See the differences in a table: "DDR4 vs DDR5," "DDR vs LPDDR vs GDDR vs HBM"
• Try the numbers: the memory bandwidth calculator (works out how much data can move from the number of lines and their speed)
• Terms for the next step: 1T1C cell (the formal name for a DRAM cell), Rowhammer (opening the same row over and over can change data in the rows next to it)
• Terms further on: CAS latency (the wait from choosing a column until data comes out), ECC (a way to find and fix errors), 3D DRAM (research on stacking cells vertically)
• See it in figures: a figure of a DRAM cell drawn with circuit symbols is in the list of figures
• Related article: "Why Are GPUs Used for AI?" (how memory speed can hold back calculation)